公开(公告)号：US11978772B2

公开(公告)日：2024-05-07

申请号：US17678460

申请日：2022-02-23

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yoshiyuki Kawashima

IPC: H01L21/28 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/792

CPC classification number: H01L29/40117 ,  H01L29/42344 ,  H01L29/66484 ,  H01L29/66833 ,  H01L29/7832 ,  H01L29/792

Abstract: A first gate electrode is formed on a semiconductor substrate via a first insulating film containing a metal element. A sidewall insulating film is formed on a side surface of the first gate electrode. A second gate electrode is formed on the semiconductor substrate via a second insulating film. The second gate electrode is formed so as to adjacent to the first gate electrode via the second insulating film. The second insulating film is made of a stacked film having a third insulating film, a fourth insulating film having a charge accumulating function, and a fifth insulating film. The third insulating film is formed on the semiconductor substrate as a result of an oxidation of a portion of the semiconductor substrate, and formed on the side surface of the first gate electrode as a result of an oxidation of the sidewall insulating film, by the thermal oxidation treatment.

公开(公告)号：US11342430B2

公开(公告)日：2022-05-24

申请号：US17084097

申请日：2020-10-29

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Digh Hisamoto ,  Yoshiyuki Kawashima ,  Takashi Hashimoto

IPC: H01L29/423 ,  H01L21/28 ,  H01L29/10 ,  H01L29/78 ,  H01L29/792 ,  H01L27/11568

Abstract: A semiconductor device has a split-gate type MONOS structure using a FinFET, and it includes a source and a drain each formed of an n-type impurity diffusion layer, a first channel forming layer which is formed under a control gate and is formed of a semiconductor layer doped with a p-type impurity, and a second channel forming layer which is formed under a memory gate and is formed of a semiconductor layer doped with an n-type impurity. Further, the semiconductor device includes a p-type semiconductor layer which is formed under the second channel forming layer and has an impurity concentration higher than an impurity concentration of a semiconductor substrate.

公开(公告)号：US11094833B2

公开(公告)日：2021-08-17

申请号：US16452261

申请日：2019-06-25

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Masao Inoue ,  Masaru Kadoshima ,  Yoshiyuki Kawashima ,  Ichiro Yamakawa

IPC: H01L29/792 ,  H01L29/423 ,  H01L29/51 ,  H01L21/28 ,  H01L21/02 ,  H01L29/66

Abstract: A memory cell, which is a nonvolatile memory cell, includes a gate dielectric film having charge storage layer capable of holding charges, and a memory gate electrode formed on the gate dielectric film. The charge storage layer includes an insulating film containing hafnium, silicon, and oxygen, an insertion layer formed on the insulating film and containing aluminum, and an insulating film formed on the insertion layer and containing hafnium, silicon, and oxygen.

公开(公告)号：US10439032B2

公开(公告)日：2019-10-08

申请号：US15978296

申请日：2018-05-14

Applicant: Renesas Electronics Corporation

Inventor： Atsushi Yoshitomi ,  Yoshiyuki Kawashima

IPC: H01L29/423 ,  H01L27/11568 ,  H01L29/66 ,  H01L29/78 ,  H01L29/792

Abstract: To provide a semiconductor device having improved reliability by relaxing the unevenness of the injection distribution of electrons and holes into a charge accumulation film attributable to the shape of the fin of a MONOS memory comprised of a fin transistor. Of a memory gate electrode configuring a memory cell formed above a fin, a portion contiguous to an ONO film that covers the upper surface of the fin and a portion contiguous to the ONO film that covers the side surface of the fin are made of electrode materials different in work function, respectively, and the boundary surface between them is located below the upper surface of the fin.

公开(公告)号：US10312254B2

公开(公告)日：2019-06-04

申请号：US15699756

申请日：2017-09-08

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Atsushi Yoshitomi ,  Yoshiyuki Kawashima

IPC: H01L27/1157 ,  H01L21/28 ,  H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L29/792 ,  H01L29/40 ,  H01L29/49

Abstract: The reliability and performances of a semiconductor device having a nonvolatile memory are improved. A control gate electrode is formed over a semiconductor substrate via a first insulation film. A memory gate electrode is formed over the semiconductor substrate via a second insulation film having a charge accumulation part. The second insulation film is formed across between the semiconductor substrate and the memory gate electrode, and between the control gate electrode and the memory gate electrode. Between the control gate electrode and the memory gate electrode, a third insulation film is formed between the second insulation film and the memory gate electrode. The third insulation film is not formed under the memory gate electrode. A part of the memory gate electrode is present under the lower end face of the third insulation film.

公开(公告)号：US09570610B2

公开(公告)日：2017-02-14

申请号：US15093048

申请日：2016-04-07

Applicant: Renesas Electronics Corporation

Inventor： Koichi Toba ,  Hiraku Chakihara ,  Yoshiyuki Kawashima ,  Kentaro Saito ,  Takashi Hashimoto

IPC: H01L29/78 ,  H01L21/285 ,  H01L29/66 ,  H01L21/28 ,  H01L21/3105 ,  H01L27/092 ,  H01L29/423 ,  H01L27/115 ,  H01L21/8234

CPC classification number: H01L29/7847 ,  H01L21/28282 ,  H01L21/28518 ,  H01L21/3105 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823468 ,  H01L27/0922 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/66825 ,  H01L29/66833

Abstract: To improve a semiconductor device having a nonvolatile memory. A first MISFET, a second MISFET, and a memory cell are formed, and a stopper film made of a silicon oxide film is formed thereover. Then, over the stopper film, a stress application film made of a silicon nitride film is formed, and the stress application film over the second MISFET and the memory cell is removed. Thereafter, heat treatment is performed to apply a stress to the first MISFET. Thus, a SMT is not applied to each of elements, but is applied selectively. This can reduce the degree of degradation of the second MISFET due to H (hydrogen) in the silicon nitride film forming the stress application film. This can also reduce the degree of degradation of the characteristics of the memory cell due to the H (hydrogen) in the silicon nitride film forming the stress application film.

Abstract translation: 改善具有非易失性存储器的半导体器件。 形成第一MISFET，第二MISFET和存储单元，并在其上形成由氧化硅膜制成的阻挡膜。 然后，在阻挡膜上形成由氮化硅膜构成的应力施加膜，除去第二MISFET和存储单元上的应力施加膜。 此后，进行热处理以向第一MISFET施加应力。 因此，SMT不应用于每个元件，而是被选择性地应用。 这可以降低由于形成应力施加膜的氮化硅膜中的H（氢）导致的第二MISFET的劣化程度。 这也可以由于形成应力施加膜的氮化硅膜中的H（氢）而降低存储单元的特性的劣化程度。

公开(公告)号：US20160260795A1

公开(公告)日：2016-09-08

申请号：US14992067

申请日：2016-01-11

Applicant: Renesas Electronics Corporation

Inventor： Satoshi Abe ,  Hiraku Chakihara ,  Kyoko Umeda ,  Yoshiyuki Kawashima ,  Kentaro Saito

IPC: H01L49/02 ,  H01L27/115

CPC classification number: H01L28/60 ,  H01L27/0629 ,  H01L27/11573

Abstract: In a semiconductor device including a nonvolatile memory, a novel stacked capacitive element is provided. The semiconductor device includes the stacked capacitive element including a first capacitive electrode made of an n-type well region formed in a semiconductor substrate, a second capacitive electrode formed so as to overlap the first capacitive electrode via a first capacitive insulating film, a third capacitive electrode formed so as to overlap the second capacitive electrode via a second capacitive insulating film, and a fourth capacitive electrode formed so as to overlap the third capacitive electrode via a third capacitive insulating film. To the first and third capacitive electrodes, a first potential is applied and, to the second and fourth capacitive electrodes, a second potential different from the first potential is applied.

Abstract translation: 在包括非易失性存储器的半导体器件中，提供了一种新颖的叠层电容元件。 半导体器件包括堆叠的电容元件，其包括由形成在半导体衬底中的n型阱区域构成的第一电容电极，经由第一电容绝缘膜形成为与第一电容电极重叠的第二电容电极，第三电容 电极，其经由第二电容绝缘膜与第二电容电极重叠形成，第四电容电极通过第三电容绝缘膜与第三电容电极重叠形成。 对于第一和第三电容电极，施加第一电位，并且向第二和第四电容电极施加不同于第一电位的第二电位。

公开(公告)号：US20160064402A1

公开(公告)日：2016-03-03

申请号：US14829638

申请日：2015-08-19

Applicant: Renesas Electronics Corporation

Inventor： Kyoko Umeda ,  Yoshiyuki Kawashima ,  Hiraku Chakihara

IPC: H01L27/115 ,  H01L21/3213 ,  H01L21/02 ,  H01L49/02 ,  H01L21/28

CPC classification number: H01L21/32135 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/022 ,  H01L27/0629 ,  H01L27/11573 ,  H01L28/40 ,  H01L28/60 ,  H01L29/42344 ,  H01L29/66833

Abstract: In method for manufacturing a semiconductor device including a nonvolatile memory, a new method for manufacturing a capacitor element is provided. After working a control gate electrode, a gate insulation film including an electric charge accumulation section, and a memory gate electrode of a memory cell, in order to protect the memory cell, a p-type well of a MISFET is formed in a state the control gate electrode, the gate insulation film, and the memory gate electrode are covered by an insulation film. Also, this insulation film is used as a capacitor insulation film of a laminated type capacitor element.

Abstract translation: 在制造包括非易失性存储器的半导体器件的方法中，提供了一种用于制造电容器元件的新方法。 为了保护存储单元，在加工了控制栅电极，包括电荷累积部分的栅极绝缘膜和存储单元的存储栅极之后，形成MISFET的p型阱，状态为 控制栅电极，栅极绝缘膜和存储栅电极被绝缘膜覆盖。 此外，该绝缘膜用作叠层型电容器元件的电容器绝缘膜。

公开(公告)号：US20160064397A1

公开(公告)日：2016-03-03

申请号：US14829605

申请日：2015-08-18

Applicant: Renesas Electronics Corporation

Inventor： Tomohiro Hayashi ,  Yoshiyuki Kawashima

IPC: H01L27/115 ,  H01L21/265 ,  H01L29/423 ,  H01L29/66 ,  H01L21/02 ,  H01L21/28 ,  H01L21/266 ,  H01L21/3213

CPC classification number: H01L27/11521 ,  H01L21/02164 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/32133 ,  H01L21/3247 ,  H01L27/11526 ,  H01L27/11568 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/42344 ,  H01L29/6656

Abstract: An improvement is achieved in the performance of a semiconductor device. In a method of manufacturing the semiconductor device, using a control gate electrode and a memory gate electrode which are formed over a semiconductor substrate as a mask, n-type impurity ions are implanted from a direction perpendicular to a main surface of the semiconductor substrate. Then, using the control gate electrode, the memory gate electrode, and first and second sidewall spacers as a mask, other n-type impurity ions are implanted from a direction inclined relative to the direction perpendicular to the main surface of the semiconductor substrate.

Abstract translation: 在半导体器件的性能方面实现了改进。 在制造半导体器件的方法中，使用形成在半导体衬底上的控制栅电极和存储栅电极作为掩模，从垂直于半导体衬底的主表面的方向注入n型杂质离子。 然后，使用控制栅电极，存储栅电极以及第一和第二侧壁间隔件作为掩模，从相对于与半导体衬底的主表面垂直的方向倾斜的方向注入其它n型杂质离子。

公开(公告)号：US20160064226A1

公开(公告)日：2016-03-03

申请号：US14829614

申请日：2015-08-18

Applicant: Renesas Electronics Corporation

Inventor： Yoshiyuki Kawashima ,  Hiraku Chakihara ,  Akio Nishida

IPC: H01L21/28 ,  H01L27/115

CPC classification number: H01L21/31053 ,  H01L21/0217 ,  H01L21/3105 ,  H01L21/31144 ,  H01L21/32133 ,  H01L21/324 ,  H01L27/11573 ,  H01L29/40117 ,  H01L29/42344 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7847

Abstract: Improvements are achieved in the properties of a semiconductor device including a MISFET and a nonvolatile memory. Over a gate electrode included in the MISFET and a control gate electrode and a memory gate electrode each included in a memory cell, a stress application film is formed of a silicon nitride film. Then, by removing the silicon nitride film from over the control gate electrode and the memory gate electrode, an opening is formed over the control gate electrode and the memory gate electrode. Then, in a state where the opening is formed in the silicon nitride film, heat treatment is performed to apply a stress to the MISFET. By thus removing the stress application film (silicon nitride film) from over the memory cell, it is possible to avoid the degradation of the properties of the memory cell due to H (hydrogen) in the silicon nitride film.

Abstract translation: 在包括MISFET和非易失性存储器的半导体器件的性能方面实现了改进。 在包括在MISFET中的栅电极和每个包括在存储单元中的控制栅电极和存储栅电极中，应力施加膜由氮化硅膜形成。 然后，通过从控制栅电极和存储栅电极上除去氮化硅膜，在控制栅电极和存储栅极上形成一个开口。 然后，在氮化硅膜中形成开口的状态下，进行热处理，向MISFET施加应力。 通过从存储单元上除去应力施加膜（氮化硅膜），可以避免由于氮化硅膜中的H（氢）导致的存储单元的性质的劣化。