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    ABNORMAL INTERRUPT REQUEST PROCESSING
    12.
    发明申请
    ABNORMAL INTERRUPT REQUEST PROCESSING 审中-公开

    公开(公告)号：US20170242809A1

    公开(公告)日：2017-08-24

    申请号：US15588246

    申请日：2017-05-05

    Applicant: RENESAS ELECTRONICS CORPORATION

    Inventor： Takuya HIRADE ,  Yukitoshi TSUBOI ,  Ryosuke OKUDA

    IPC: G06F13/24 ,  G06F11/22

    CPC classification number: G06F13/24 ,  G06F11/2231 ,  G06F11/2273 ,  Y02D10/14

    Abstract: To detect an abnormality in an interrupt control system without completely depending on dualization of a circuit, without the need to create a test pattern for a built-in self-test by spending time, and without considerably increasing an amount of power consumption. A test interrupt request is generated periodically using a timer or the like in an interrupt signal system from an interrupt controller to a central processing unit, the state of an interrupt request flag within the interrupt controller is checked in an interrupt processing routine, and in the case where it is detected that the same interrupt request flag is kept in a set state twice or more in succession, it is supposed that there is a high possibility that a failure has occurred in the interrupt signal system and it is considered that there is an abnormality.

    Data Processing Apparatus
    14.
    发明申请
    Data Processing Apparatus 有权
    数据处理装置

    公开(公告)号：US20150194984A1

    公开(公告)日：2015-07-09

    申请号：US14590913

    申请日：2015-01-06

    Applicant: Renesas Electronics Corporation

    Inventor： Yukitoshi TSUBOI ,  Hideo NAGANO

    IPC: H03M13/29

    CPC classification number: H03M13/2927 ,  G06F11/1012 ,  G06F11/1044 ,  G06F11/1052 ,  H03M13/095 ,  H03M13/11 ,  H03M13/13 ,  H03M13/1575 ,  H03M13/19 ,  H03M13/29 ,  H03M13/3715 ,  H03M13/6575

    Abstract: A data processing apparatus including a processor and a memory has a parity/ECC encoder circuit and a parity/ECC decoder circuit. The parity/ECC encoder circuit is disposed in a signal path for writing data to the memory, includes a parity generating circuit for generating a parity of a plurality of bits from data to be written, and writes the generated parity together with the data into the memory. The parity/ECC decoder circuit is disposed in a signal path for reading data from the memory and includes a parity check unit. The parity generating circuit is configured so that each of a plurality of bits configuring the data contributes to generation of a parity of at least two bits. Consequently, the parity check unit can detect a two-bit error at high speed.

    Abstract translation: 包括处理器和存储器的数据处理装置具有奇偶校验/ ECC编码器电路和奇偶校验/ ECC解码器电路。 奇偶校验/ ECC编码器电路设置在用于将数据写入存储器的信号路径中，包括奇偶校验生成电路，用于从要写入的数据生成多个比特的奇偶校验，并将生成的奇偶校验与数据一起写入到 记忆。 奇偶校验/ ECC解码器电路设置在用于从存储器读取数据的信号路径中，并且包括奇偶校验单元。 奇偶生成电路被配置为使得构成数据的多个比特中的每一个有助于生成至少两个比特的奇偶校验。 因此，奇偶校验单元可以高速检测两位错误。

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