公开(公告)号：US6057558A

公开(公告)日：2000-05-02

申请号：US34344

申请日：1998-03-04

申请人： Tsuyoshi Yamamoto ,  Rajesh Kumar ,  Kunihiko Hara ,  Yuichi Takeuchi ,  Kazukuni Hara ,  Masami Naito

发明人： Tsuyoshi Yamamoto ,  Rajesh Kumar ,  Kunihiko Hara ,  Yuichi Takeuchi ,  Kazukuni Hara ,  Masami Naito

IPC分类号： H01L21/04 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/24 ,  H01L29/423 ,  H01L29/78 ,  H01L31/0312

CPC分类号： H01L29/0847 ,  H01L29/0626 ,  H01L29/42368 ,  H01L29/66068 ,  H01L29/66666 ,  H01L29/7828 ,  H01L29/045 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/4236 ,  H01L29/4238

摘要： In a silicon carbide semiconductor device such as a trench gate type power MOSFET, the film thickness and the impurity concentration of a thin film silicon carbide semiconductor layer formed on a trench side face to constitute an accumulation-type channel-forming region and enable the device to operate with a low gate voltage, low on-resistance and low power loss are set so that on impression of a reverse bias voltage a pn junction between a P-type epitaxial layer and an n.sup.- -type epitaxial layer undergoes avalanche breakdown before the thin film silicon carbide semiconductor layer undergoes punch-through. By this means it is possible to obtain a target high source-drain withstand voltage.

摘要翻译： 在诸如沟槽栅型功率MOSFET的碳化硅半导体器件中，形成在沟槽侧面上的薄膜碳化硅半导体层的膜厚度和杂质浓度构成积聚型沟道形成区域，并使器件 以低栅极电压操作，设置低导通电阻和低功率损耗，使得在反向偏置电压的印象上，P型外延层和n型外延层之间的pn结在其之前经历雪崩击穿 薄膜碳化硅半导体层进行穿通。 通过这种方式，可以获得目标高的源极 - 漏极耐受电压。

公开(公告)号：US6054752A

公开(公告)日：2000-04-25

申请号：US107507

申请日：1998-06-30

申请人： Kazukuni Hara ,  Yuichi Takeuchi ,  Tsuyoshi Yamamoto ,  Rajesh Kumar ,  Mitsuhiro Kataoka

发明人： Kazukuni Hara ,  Yuichi Takeuchi ,  Tsuyoshi Yamamoto ,  Rajesh Kumar ,  Mitsuhiro Kataoka

IPC分类号： H01L21/04 ,  H01L29/06 ,  H01L29/24 ,  H01L29/78 ,  H01L29/34 ,  H01L29/40

CPC分类号： H01L29/7813 ,  H01L29/0611 ,  H01L29/0638 ,  H01L29/66068 ,  H01L29/7802 ,  H01L29/1608

摘要： A semiconductor device comprises a semiconductor substrate including a first conductivity type first semiconductor layer and a second conductivity type second semiconductor layer formed on the first semiconductor layer. A unit cell for controlling current flowing between a source electrode and a drain electrode is formed in the semiconductor substrate. A trench is formed in a peripheral region of the unit cell to form mesa structure. A field relaxing layer is formed between an insulating film on a side face of the second trench and both the first semiconductor layer and the second semiconductor layer in order to relax concentration of an electric field in the insulating film.

摘要翻译： 半导体器件包括：半导体衬底，包括形成在第一半导体层上的第一导电型第一半导体层和第二导电型第二半导体层。 在半导体衬底中形成用于控制在源电极和漏电极之间流动的电流的单元。 在单电池的周边区域形成沟槽，形成台面结构。 在第二沟槽的侧面上的绝缘膜与第一半导体层和第二半导体层之间形成场弛豫层，以使绝缘膜中的电场的集中化。

公开(公告)号：US20060071217A1

公开(公告)日：2006-04-06

申请号：US11206271

申请日：2005-08-18

申请人： Takasumi Ohyanagi ,  Atsuo Watanabe ,  Toshio Sakakibara ,  Tsuyoshi Yamamoto ,  Hiroki Nakamura

发明人： Takasumi Ohyanagi ,  Atsuo Watanabe ,  Toshio Sakakibara ,  Tsuyoshi Yamamoto ,  Hiroki Nakamura

IPC分类号： H01L31/0312

CPC分类号： H01L21/823487 ,  H01L29/7722

摘要： A semiconductor device includes a vertical field-effect transistor having a substrate of first conduction type in a substrate base, a drain electrode formed on a first surface of the substrate, an epitaxial layer of first conduction type formed on a second surface of the substrate, a source region of first conduction type formed on the semiconductor base, a source ohmic contact metal film in ohmic contact with the source region, trenches formed from the second surface of the semiconductor base, and a gate region of second conduction type formed along the trenches. The semiconductor device further includes a gate rise metal film in ohmic contact with the draw-out layer of the gate region on the bottom of the trenches and rising to the second surface of the semiconductor base, and a gate draw-out metal film connected to the gate rise metal film from the second surface of the semiconductor base.

摘要翻译： 半导体器件包括：垂直场效应晶体管，其具有在基板基底中的第一导电类型的衬底;形成在衬底的第一表面上的漏电极，形成在衬底的第二表面上的第一导电类型的外延层; 在半导体基底上形成的第一导电类型的源极区域，与源极区欧姆接触的源欧姆接触金属膜，从半导体基底的第二表面形成的沟槽和沿着沟槽形成的第二导电类型的栅极区域 。 半导体器件还包括与沟槽底部的栅极区域的引出层欧姆接触并上升到半导体基底的第二表面的栅极上升金属膜，以及连接到 来自半导体基底的第二表面的栅极上升金属膜。

公开(公告)号：US07855384B2

公开(公告)日：2010-12-21

申请号：US11783611

申请日：2007-04-10

申请人： Tsuyoshi Yamamoto ,  Toshio Sakakibara ,  Hiroki Nakamura ,  Toshiyuki Morishita ,  Takasumi Ooyanagi ,  Atsuo Watanabe

发明人： Tsuyoshi Yamamoto ,  Toshio Sakakibara ,  Hiroki Nakamura ,  Toshiyuki Morishita ,  Takasumi Ooyanagi ,  Atsuo Watanabe

IPC分类号： H01L29/04 ,  H01L29/94

CPC分类号： H01L29/1608 ,  H01L29/0843 ,  H01L29/1066 ,  H01L29/8083 ,  H01L29/872

摘要： A SiC semiconductor device includes: a SiC substrate having a drain layer, a drift layer and a source layer stacked in this order; multiple trenches penetrating the source layer and reaching the drift layer; a gate layer on a sidewall of each trench; an insulation film on the sidewall of each trench covering the gate layer; a source electrode on the source layer; and a diode portion in or under the trench contacting the drift layer to provide a diode. The drift layer between the gate layer on the sidewalls of adjacent two trenches provides a channel region. The diode portion is coupled with the source electrode, and insulated from the gate layer with the insulation film.

摘要翻译： SiC半导体器件包括：具有漏极层，漂移层和源极层的SiC衬底; 多个沟槽穿透源层并到达漂移层; 每个沟槽的侧壁上的栅极层; 覆盖所述栅极层的每个沟槽的侧壁上的绝缘膜; 源极上的源电极; 以及与沟槽接触的沟槽中或下方的二极管部分，以提供二极管。 相邻两个沟槽的侧壁上的栅极层之间的漂移层提供沟道区域。 二极管部分与源电极耦合，并与绝缘膜与栅极层绝缘。

公开(公告)号：US07663181B2

公开(公告)日：2010-02-16

申请号：US11206271

申请日：2005-08-18

申请人： Takasumi Ohyanagi ,  Atsuo Watanabe ,  Toshio Sakakibara ,  Tsuyoshi Yamamoto ,  Hiroki Nakamura

发明人： Takasumi Ohyanagi ,  Atsuo Watanabe ,  Toshio Sakakibara ,  Tsuyoshi Yamamoto ,  Hiroki Nakamura

IPC分类号： H01L29/72

CPC分类号： H01L21/823487 ,  H01L29/7722

摘要： A semiconductor device includes a vertical field-effect transistor having a substrate of first conduction type in a substrate base, a drain electrode formed on a first surface of the substrate, an epitaxial layer of first conduction type formed on a second surface of the substrate, a source region of first conduction type formed on the semiconductor base, a source ohmic contact metal film in ohmic contact with the source region, trenches formed from the second surface of the semiconductor base, and a gate region of second conduction type formed along the trenches. The semiconductor device further includes a gate rise metal film in ohmic contact with the draw-out layer of the gate region on the bottom of the trenches and rising to the second surface of the semiconductor base, and a gate draw-out metal film connected to the gate rise metal film from the second surface of the semiconductor base.

摘要翻译： 半导体器件包括：垂直场效应晶体管，其具有在基板基底中的第一导电类型的衬底;形成在衬底的第一表面上的漏电极，形成在衬底的第二表面上的第一导电类型的外延层; 在半导体基底上形成的第一导电类型的源极区域，与源极区欧姆接触的源欧姆接触金属膜，从半导体基底的第二表面形成的沟槽和沿着沟槽形成的第二导电类型的栅极区域 。 半导体器件还包括与沟槽底部的栅极区域的引出层欧姆接触并上升到半导体基底的第二表面的栅极上升金属膜，以及连接到 来自半导体基底的第二表面的栅极上升金属膜。

公开(公告)号：US20060076613A1

公开(公告)日：2006-04-13

申请号：US11206212

申请日：2005-08-18

申请人： Takasumi Ohyanagi ,  Atsuo Watanabe ,  Toshio Sakakibara ,  Tsuyoshi Yamamoto ,  Hiroki Nakamura ,  Rajesh Malhan

发明人： Takasumi Ohyanagi ,  Atsuo Watanabe ,  Toshio Sakakibara ,  Tsuyoshi Yamamoto ,  Hiroki Nakamura ,  Rajesh Malhan

IPC分类号： H01L29/94

CPC分类号： H01L29/1066 ,  H01L29/7722 ,  H01L29/8083

摘要： A semiconductor device includes (a) a vertical field effect transistor, the vertical field effect transistor including a drain electrode formed on a first surface of a first conductivity type of a semiconductor, a pair of first trenches formed from a second surface of the semiconductor, control regions of a second conductivity type formed respectively along the first trenches, a source region of the first conductivity type formed along the second surface of the semiconductor between the first trenches, a source electrode joined to the source region, and a gate electrode adjacent to the control regions, (b) a pair of second trenches formed from the second surface of the semiconductor independently of the field effect transistor, (c) control regions of the second conductivity type formed along the second trenches, and (d) a diode having a junction formed on the second surface between the second trenches.

摘要翻译： 半导体器件包括（a）垂直场效应晶体管，垂直场效应晶体管包括形成在第一导电类型的半导体的第一表面上的漏电极，由半导体的第二表面形成的一对第一沟槽， 沿着第一沟槽分别形成的第二导电类型的控制区域，沿着第一沟槽之间的半导体的第二表面形成的第一导电类型的源极区域，与源极区域连接的源极电极和与源极区域相邻的栅电极 控制区域，（b）与场效应晶体管独立地由半导体的第二表面形成的一对第二沟槽，（c）沿着第二沟槽形成的第二导电类型的控制区，以及（d）二极管， 在第二沟槽之间的第二表面上形成的结。

公开(公告)号：US20070241338A1

公开(公告)日：2007-10-18

申请号：US11783611

申请日：2007-04-10

申请人： Tsuyoshi Yamamoto ,  Toshio Sakakibara ,  Hiroki Nakamura ,  Toshiyuki Morishita ,  Takasumi Ooyanagi ,  Atsuo Watanabe

发明人： Tsuyoshi Yamamoto ,  Toshio Sakakibara ,  Hiroki Nakamura ,  Toshiyuki Morishita ,  Takasumi Ooyanagi ,  Atsuo Watanabe

IPC分类号： H01L31/0312

CPC分类号： H01L29/1608 ,  H01L29/0843 ,  H01L29/1066 ,  H01L29/8083 ,  H01L29/872

摘要： A SiC semiconductor device includes: a SiC substrate having a drain layer, a drift layer and a source layer stacked in this order; multiple trenches penetrating the source layer and reaching the drift layer; a gate layer on a sidewall of each trench; an insulation film on the sidewall of each trench covering the gate layer; a source electrode on the source layer; and a diode portion in or under the trench contacting the drift layer to provide a diode. The drift layer between the gate layer on the sidewalls of adjacent two trenches provides a channel region. The diode portion is coupled with the source electrode, and insulated from the gate layer with the insulation film.

摘要翻译： SiC半导体器件包括：具有漏极层，漂移层和源极层的SiC衬底; 多个沟槽穿透源层并到达漂移层; 每个沟槽的侧壁上的栅极层; 覆盖所述栅极层的每个沟槽的侧壁上的绝缘膜; 源极上的源电极; 以及与沟槽接触的沟槽中或下方的二极管部分，以提供二极管。 相邻两个沟槽的侧壁上的栅极层之间的漂移层提供沟道区域。 二极管部分与源电极耦合，并与绝缘膜与栅极层绝缘。

公开(公告)号：US20130005318A1

公开(公告)日：2013-01-03

申请号：US13519702

申请日：2010-12-27

申请人： Masayuki Motegi ,  Yoshitsugu Shimazu ,  Hidehiko Oyane ,  Tsuyoshi Yamamoto

发明人： Masayuki Motegi ,  Yoshitsugu Shimazu ,  Hidehiko Oyane ,  Tsuyoshi Yamamoto

IPC分类号： H04W4/00

CPC分类号： H04W24/08 ,  H04W88/10 ,  H04W92/12

摘要： In a BRE300, an RF interface for transmitting and receiving an RF signal is used for communication with a MDE 200 and a digital signal interface for transmitting and receiving a digital signal in accordance with CPRI is used for communication with BDE 300. The BRE 300 includes a monitoring signal interface configured to notify the MDE 200 of a monitoring signal indicating a state of the radio unit 50. The signal transmitted and received through the monitoring signal interface is a ground signal and is of type different from types of signals transmitted and received by the RF interface and the digital signal interface.

摘要翻译： 在BRE300中，用于发送和接收RF信号的RF接口用于与MDE 200进行通信，并且用于根据CPRI发送和接收数字信号的数字信号接口用于与BDE 300进行通信。BRE 300包括 监视信号接口，被配置为向MDE 200通知指示无线电单元50的状态的监视信号。通过监视信号接口发送和接收的信号是接地信号，并且类型与由信号发送和接收的信号的类型不同 RF接口和数字信号接口。

公开(公告)号：US08285088B2

公开(公告)日：2012-10-09

申请号：US12068351

申请日：2008-02-05

申请人： Hirofumi Aota ,  Kohei Shibata ,  Tsuyoshi Yamamoto

发明人： Hirofumi Aota ,  Kohei Shibata ,  Tsuyoshi Yamamoto

IPC分类号： G02B6/12 ,  G02B6/34 ,  G02B7/02

CPC分类号： G02B6/29311 ,  G02B6/29313 ,  G02B6/3512 ,  G02B6/3548 ,  G02B6/356 ,  G02B6/3586 ,  H04J14/0201

摘要： A wavelength selective switch for suppressing degradation of pass band characteristics when the temperature rises. The wavelength selective switch includes a spectroscopic element for separating input light and providing angular dispersion depending on wavelengths, a collective lens for gathering light output from the spectroscopic element, and a movable reflection block which includes a plurality of mirrors arranged in the direction of angular dispersion made by the spectroscopic element, changes the angles of the mirrors in a direction differing from the direction of angular dispersion, and reflects the light coming from the collective lens. The collective lens is fixed at one end with respect to the direction of angular dispersion, expands with heat in a direction in which it is not fixed when the temperature rises, and outputs the light in a direction opposite to the direction in which the angle of light output from the spectroscopic element changes.

摘要翻译： 一种用于当温度升高时抑制通带特性劣化的波长选择开关。 波长选择开关包括用于分离输入光并提供取决于波长的角度色散的分光元件，用于聚集从分光元件输出的光的集体透镜，以及可移动反射块，其包括沿角度分散方向布置的多个反射镜 由分光元件制成的反射镜的角度沿与角度分散方向不同的方向改变，并且反射来自聚光透镜的光。 集体透镜相对于角度分散的方向固定在一端，当温度升高时，其在不固定的方向上以热量方式膨胀，并且沿与该角度的方向相反的方向输出光 分光元件的光输出变化。

公开(公告)号：US08232125B2

公开(公告)日：2012-07-31

申请号：US12457677

申请日：2009-06-18

申请人： Nobuaki Hatori ,  Tsuyoshi Yamamoto ,  Hisao Sudo ,  Yasuhiko Arakawa

发明人： Nobuaki Hatori ,  Tsuyoshi Yamamoto ,  Hisao Sudo ,  Yasuhiko Arakawa

IPC分类号： H01L21/00

CPC分类号： H01S5/22 ,  B82Y20/00 ,  H01S5/028 ,  H01S5/06226 ,  H01S5/0655 ,  H01S5/3086 ,  H01S5/3412 ,  H01S5/34306 ,  H01S5/34353 ,  H01S2301/18

摘要： An active layer having a p-type quantum dot structure is disposed over a lower cladding layer made of semiconductor material of a first conductivity type. An upper cladding layer is disposed over the active layer. The upper cladding layer is made of semiconductor material, and includes a ridge portion and a cover portion. The ridge portion extends in one direction, and the cover portion covers the surface on both sides of the ridge portion. A capacitance reducing region is disposed on both sides of the ridge portion and reaching at least the lower surface of the cover portion. The capacitance reducing region has the first conductivity type or a higher resistivity than that of the ridge portion, and the ridge portion has a second conductivity type. If the lower cladding layer is an n-type, the capacitance reducing region reaches at least the upper surface of the lower cladding layer.

摘要翻译： 具有p型量子点结构的有源层设置在由第一导电类型的半导体材料制成的下包层上。 上覆层设置在有源层上。 上包层由半导体材料制成，并且包括脊部和盖部。 脊部沿一个方向延伸，并且盖部分覆盖脊部两侧的表面。 电容减小区域设置在脊部的两侧并且至少到达盖部的下表面。 电容减小区域具有比脊部分的第一导电类型或更高的电阻率，并且脊部分具有第二导电类型。 如果下包层为n型，则电容减小区域至少到达下包层的上表面。