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公开(公告)号：US10798322B2
公开(公告)日：2020-10-06
申请号：US16140862
申请日：2018-09-25
Applicant: Rambus Inc.
Inventor： Craig M. Smith , Frank Armstrong , Jay Endsley , Thomas Vogelsang , James E. Harris , John Ladd , Michael Guidash
Abstract: A pixel array within an integrated-circuit image sensor is exposed to light representative of a scene during a first frame interval and then oversampled a first number of times within the first frame interval to generate a corresponding first number of frames of image data from which a first output image may be constructed. One or more of the first number of frames of image data are evaluated to determine whether a range of luminances in the scene warrants adjustment of an oversampling factor from the first number to a second number, if so, the oversampling factor is adjusted such that the pixel array is oversampled the second number of times within a second frame interval to generate a corresponding second number of frames of image data from which a second output image may be constructed.
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公开(公告)号：US10388337B2
公开(公告)日：2019-08-20
申请号：US15889191
申请日：2018-02-05
Applicant: Rambus Inc.
Inventor： James E. Harris , Thomas Vogelsang , Frederick A. Ware , Ian P. Shaeffer
IPC: G11C7/00 , G11C7/10 , G11C5/02 , G11C11/4076 , G11C11/408 , G11C11/4091 , G11C7/06 , G11C7/08 , G11C7/12 , G11C7/22 , G11C8/08 , G11C8/10
Abstract: Row activation operations within a memory component are carried out with respect to subrows instead of complete storage rows to reduce power consumption. Further, instead of activating subrows in response to row commands, subrow activation operations are deferred until receipt of column commands that specify the column operation to be performed and the subrow to be activated.
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公开(公告)号：US20170178702A1
公开(公告)日：2017-06-22
申请号：US15390674
申请日：2016-12-26
Applicant: Rambus Inc.
Inventor： James E. Harris , Thomas Vogelsang , Frederick A. Ware , Ian P. Shaeffer
CPC classification number: G11C7/1039 , G11C5/025 , G11C7/06 , G11C7/065 , G11C7/08 , G11C7/12 , G11C7/222 , G11C8/08 , G11C8/10 , G11C11/4076 , G11C11/4087 , G11C11/4091
Abstract: Row activation operations within a memory component are carried out with respect to subrows instead of complete storage rows to reduce power consumption. Further, instead of activating subrows in response to row commands, subrow activation operations are deferred until receipt of column commands that specify the column operation to be performed and the subrow to be activated.
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公开(公告)号：US09681071B2
公开(公告)日：2017-06-13
申请号：US15333645
申请日：2016-10-25
Applicant: Rambus Inc.
Inventor： Craig M. Smith , Michael Guidash , Jay Endsley , Thomas Vogelsang , James E. Harris
IPC: H04N3/14 , H04N5/335 , H04N5/355 , H04N5/347 , H04N5/374 , H04N5/378 , H04N5/3745 , H01L27/146 , H01L31/062 , H01L31/113
CPC classification number: H04N5/3559 , H01L27/14621 , H01L27/14627 , H01L27/14641 , H01L27/14643 , H01L27/14645 , H04N5/347 , H04N5/355 , H04N5/3741 , H04N5/37455 , H04N5/378
Abstract: In a pixel array within an integrated-circuit image sensor, each of a plurality of pixels is evaluated to determine whether charge integrated within the pixel in response to incident light exceeds a first threshold. N-bit digital samples corresponding to the charge integrated within at least a subset of the plurality of pixels are generated, and then applied to a lookup table to retrieve respective M-bit digital values (M being less than N), wherein a stepwise range of charge integration levels represented by possible states of the M-bit digital values extends upward from a starting charge integration level that is determined based on the first threshold.
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公开(公告)号：US09432597B2
公开(公告)日：2016-08-30
申请号：US14807794
申请日：2015-07-23
Applicant: Rambus Inc.
Inventor： Michael Guidash , Thomas Vogelsang , Jay Endsley , James E. Harris , Craig M. Smith , John Ladd , Michael T. Ching
IPC: H04N5/365 , H04N5/378 , H04N5/357 , H04N5/3745 , H04N5/355
CPC classification number: H04N5/3655 , H04N5/355 , H04N5/357 , H04N5/3575 , H04N5/3651 , H04N5/3698 , H04N5/3745 , H04N5/37455 , H04N5/378
Abstract: An integrated-circuit image sensor generates, as constituent reference voltages of a first voltage ramp, a first sequence of linearly related reference voltages followed by a second sequence of exponentially related reference voltages. The integrated-circuit image sensor compares the constituent reference voltages of the first voltage ramp with a first signal level representative of photocharge integrated within a pixel of the image sensor to identify a first reference voltage of the constituent reference voltages that is exceeded by the first signal level.
Abstract translation: 作为第一电压斜坡的组成参考电压的集成电路图像传感器产生第二线性相关参考电压序列，随后是第二指数相关参考电压序列。 集成电路图像传感器将第一电压斜坡的构成参考电压与表示在图像传感器的像素内集成的光电荷的第一信号电平进行比较，以识别由第一信号超过的构成参考电压的第一参考电压 水平。
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Patent Agency Ranking
公开(公告)号：US20160028974A1
公开(公告)日：2016-01-28
申请号：US14807794
申请日：2015-07-23
Applicant: Rambus Inc.
Inventor： Michael Guidash , Thomas Vogelsang , Jay Endsley , James E. Harris , Craig M. Smith , John Ladd , Michael T. Ching
CPC classification number: H04N5/3655 , H04N5/355 , H04N5/357 , H04N5/3575 , H04N5/3651 , H04N5/3698 , H04N5/3745 , H04N5/37455 , H04N5/378
Abstract: An integrated-circuit image sensor generates, as constituent reference voltages of a first voltage ramp, a first sequence of linearly related reference voltages followed by a second sequence of exponentially related reference voltages. The integrated-circuit image sensor compares the constituent reference voltages of the first voltage ramp with a first signal level representative of photocharge integrated within a pixel of the image sensor to identify a first reference voltage of the constituent reference voltages that is exceeded by the first signal level
Abstract translation: 作为第一电压斜坡的组成参考电压的集成电路图像传感器产生第二线性相关参考电压序列，随后是第二指数相关参考电压序列。 集成电路图像传感器将第一电压斜坡的构成参考电压与表示在图像传感器的像素内集成的光电荷的第一信号电平进行比较，以识别由第一信号超过的构成参考电压的第一参考电压 水平
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公开(公告)号：US20150201142A1
公开(公告)日：2015-07-16
申请号：US14638161
申请日：2015-03-04
Applicant: Rambus Inc.
Inventor： Craig M. Smith , Michael Guidash , Jay Endsley , Thomas Vogelsang , James E. Harris
IPC: H04N5/378
CPC classification number: H04N5/3559 , H01L27/14621 , H01L27/14627 , H01L27/14641 , H01L27/14643 , H01L27/14645 , H04N5/347 , H04N5/355 , H04N5/3741 , H04N5/37455 , H04N5/378
Abstract: In a pixel array within an integrated-circuit image sensor, each of a plurality of pixels is evaluated to determine whether charge integrated within the pixel in response to incident light exceeds a first threshold. N-bit digital samples corresponding to the charge integrated within at least a subset of the plurality of pixels are generated, and then applied to a lookup table to retrieve respective M-bit digital values (M being less than N), wherein a stepwise range of charge integration levels represented by possible states of the M-bit digital values extends upward from a starting charge integration level that is determined based on the first threshold.
Abstract translation: 在集成电路图像传感器内的像素阵列中，评估多个像素中的每一个以确定响应于入射光在像素内积分的电荷是否超过第一阈值。 产生与集成在多个像素的至少一个子集中的电荷相对应的N位数字样本，然后将其应用于查找表以检索相应的M位数字值（M小于N），其中步长范围 由M位数字值的可能状态表示的电荷积分电平从基于第一阈值确定的起始电荷积分电平向上延伸。
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公开(公告)号：US12190990B2
公开(公告)日：2025-01-07
申请号：US18373162
申请日：2023-09-26
Applicant: Rambus Inc.
Inventor： James E. Harris , Thomas Vogelsang , Frederick A. Ware , Ian P. Shaeffer
IPC: G11C7/00 , G11C5/02 , G11C7/06 , G11C7/08 , G11C7/10 , G11C7/12 , G11C7/22 , G11C8/08 , G11C8/10 , G11C11/4076 , G11C11/408 , G11C11/4091
Abstract: Row activation operations within a memory component are carried out with respect to subrows instead of complete storage rows to reduce power consumption. Further, instead of activating subrows in response to row commands, subrow activation operations are deferred until receipt of column commands that specify the column operation to be performed and the subrow to be activated.
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公开(公告)号：US20230360695A1
公开(公告)日：2023-11-09
申请号：US18203591
申请日：2023-05-30
Applicant: Rambus Inc.
Inventor： Frederick A. Ware , James E. Harris
IPC: G11C11/4093 , G11C5/04 , G11C5/06 , G11C8/12 , G11C7/22
CPC classification number: G11C11/4093 , G11C5/04 , G11C5/063 , G11C8/12 , G11C7/22
Abstract: A memory module with multiple memory devices includes a buffer system that manages communication between a memory controller and the memory devices. Each memory device supports an access mode and a low-power mode, the latter used to save power for devices that are not immediately needed. The module provides granular power management using a chip-select decoder that decodes chip-select signals from the memory controller into power-state signals that determine which of the memory devices are in which of the modes. Devices can thus be brought out of the low-power mode in relatively small numbers, as needed, to limit power consumption.
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公开(公告)号：US11804250B2
公开(公告)日：2023-10-31
申请号：US17665760
申请日：2022-02-07
Applicant: Rambus Inc.
Inventor： James E. Harris , Thomas Vogelsang , Frederick A. Ware , Ian P. Shaeffer
IPC: G11C7/00 , G11C7/10 , G11C7/08 , G11C5/02 , G11C11/4076 , G11C11/408 , G11C11/4091 , G11C7/06 , G11C7/12 , G11C7/22 , G11C8/08 , G11C8/10
CPC classification number: G11C7/1039 , G11C5/025 , G11C7/06 , G11C7/065 , G11C7/08 , G11C7/12 , G11C7/222 , G11C8/08 , G11C8/10 , G11C11/4076 , G11C11/4087 , G11C11/4091
Abstract: Row activation operations within a memory component are carried out with respect to subrows instead of complete storage rows to reduce power consumption. Further, instead of activating subrows in response to row commands, subrow activation operations are deferred until receipt of column commands that specify the column operation to be performed and the subrow to be activated.
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