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公开(公告)号：US20220262412A1
公开(公告)日：2022-08-18
申请号：US17665760
申请日：2022-02-07
Applicant: Rambus Inc.
Inventor： James E. Harris , Thomas Vogelsang , Frederick A. Ware , Ian P. Shaeffer
IPC: G11C7/10 , G11C7/08 , G11C5/02 , G11C11/4076 , G11C11/408 , G11C11/4091 , G11C7/06 , G11C7/12 , G11C7/22 , G11C8/08 , G11C8/10
Abstract: Row activation operations within a memory component are carried out with respect to subrows instead of complete storage rows to reduce power consumption. Further, instead of activating subrows in response to row commands, subrow activation operations are deferred until receipt of column commands that specify the column operation to be performed and the subrow to be activated.
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公开(公告)号：US11227639B2
公开(公告)日：2022-01-18
申请号：US17135138
申请日：2020-12-28
Applicant: Rambus Inc.
Inventor： Thomas Vogelsang
IPC: G11C5/06 , H01L23/48 , H01L27/108 , H01L25/065 , G11C5/02
Abstract: A memory device includes a first dynamic random access memory (DRAM) integrated circuit (IC) chip including first memory core circuitry, and first input/output (I/O) circuitry. A second DRAM IC chip is stacked vertically with the first DRAM IC chip. The second DRAM IC chip includes second memory core circuitry, and second I/O circuitry. Solely one of the first DRAM IC chip or the second DRAM IC chip includes a conductive path that electrically couples at least one of the first memory core circuitry or the second memory core circuitry to solely one of the first I/O circuitry or the second I/O circuitry, respectively.
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公开(公告)号：US10706913B2
公开(公告)日：2020-07-07
申请号：US16261937
申请日：2019-01-30
Applicant: Rambus Inc.
Inventor： Frederick A. Ware , John Eric Linstadt , Thomas Vogelsang
IPC: G11C7/10 , G11C11/4093 , G11C11/4094 , G11C11/4076 , G11C11/4097
Abstract: A memory stack comprises at least two memory components. The memory components have a first data link interface and are to transmit signals on a data link coupled to the first data link interface at a first voltage level. A buffer component has a second data link interface coupled to the data link. The buffer component is to receive signals on the second data link interface at the first voltage level. A level shifting latch produces a second voltage level in response to receiving the signals at the second data link interface, where the second voltage level is higher than the first voltage level.
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公开(公告)号：US10659715B2
公开(公告)日：2020-05-19
申请号：US16503391
申请日：2019-07-03
Applicant: Rambus Inc.
Inventor： Jay Endsley , Thomas Vogelsang , Craig M. Smith , Michael Guidash , Alexander C. Schneider
Abstract: Signals representative of total photocharge integrated within respective image-sensor pixels are read out of the pixels after a first exposure interval that constitutes a first fraction of a frame interval. Signals in excess of a threshold level are read out of the pixels after an ensuing second exposure interval that constitutes a second fraction of the frame interval, leaving residual photocharge within the pixels. After a third exposure interval that constitutes a third fraction of the frame interval, signals representative of a combination of at least the residual photocharge and photocharge integrated within the pixels during the third exposure interval are read out of the pixels.
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公开(公告)号：US20180124343A1
公开(公告)日：2018-05-03
申请号：US15563875
申请日：2016-03-31
Applicant: Rambus Inc.
Inventor： Thomas Vogelsang , Jay Endsley , Michael Guidash , Craig M. Smith
IPC: H04N5/378 , H04N5/353 , H04N5/355 , H01L27/146
CPC classification number: H04N5/378 , H01L27/14634 , H04N5/3532 , H04N5/3535 , H04N5/35572 , H04N5/35581 , H04N5/357 , H04N5/369
Abstract: Multiple image data subframes corresponding to respective portions of an exposure interval are generated within a sensor device of an image system. Depending on whether the exposure interval exceeds one or more exposure time thresholds, data representative multiple image data subframes are output from the image sensor device in one of at least two formats, including a first format in which each of the subframes of image data is output in its entirety, and a second format in which a logical combination of at least two of the subframes of image data is output instead of the at least two of the subframes of image data such that the total volume of image data output from the image sensor device is reduced relative to the first format.
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Patent Agency Ranking
公开(公告)号：US20170324920A1
公开(公告)日：2017-11-09
申请号：US15497093
申请日：2017-04-25
Applicant: Rambus Inc.
Inventor： Thomas Vogelsang , MIchael Guidash , Song Xue , James E. Harris
IPC: H04N5/378 , H04N5/335 , H04N5/355 , H04N5/376 , H04N5/3745
CPC classification number: H04N5/378 , H04N5/3355 , H04N5/35536 , H04N5/35545 , H04N5/35554 , H04N5/3559 , H04N5/37455 , H04N5/3765 , H04N5/379
Abstract: An image sensor architecture with multi-bit sampling is implemented within an image sensor system. A pixel signal produced in response to light incident upon a photosensitive element is converted to a multiple-bit digital value representative of the pixel signal. If the pixel signal exceeds a sampling threshold, the photosensitive element is reset. During an image capture period, digital values associated with pixel signals that exceed a sampling threshold are accumulated into image data.
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公开(公告)号：US20170230575A1
公开(公告)日：2017-08-10
申请号：US15423892
申请日：2017-02-03
Applicant: Rambus Inc.
Inventor： Jay Endsley , Thomas Vogelsang
CPC classification number: G02B5/1871 , G02B5/1842 , H04N5/335
Abstract: An imaging device uses a grating to produce an interference pattern for capture by a photodetector array. Digital photographs and other image information can then be extracted from the pattern. An integrated processor locally supports this extraction by upsampling the captured interference pattern and deconvolving the upsampled pattern with an image-calculation parameter set that represents the grating at a resolution greater than that provided by the photodetector array. Deconvolving the upsampled pattern with a high-resolution parameter increases the resolution of extracted image information.
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公开(公告)号：US20170229190A1
公开(公告)日：2017-08-10
申请号：US15393634
申请日：2016-12-29
Applicant: RAMBUS INC.
Inventor： Thomas Vogelsang , William Ng , Frederick A. Ware
CPC classification number: G11C29/025 , G01R31/2851 , G01R31/2853 , G11C5/02 , G11C5/06 , G11C8/10 , G11C29/04 , H01L22/34 , H01L25/0657 , H01L2224/16146 , H01L2225/06513 , H01L2225/06541 , H01L2924/10253 , H01L2924/1434 , H01L2924/00
Abstract: Embodiments generally relate to integrated circuit devices having through silicon vias (TSVs). In one embodiment, an integrated circuit (IC) device includes a field of TSVs and an address decoder that selectably couples at least one of the TSVs to at least one of a test input and a test evaluation circuit. In another embodiment, a method includes selecting one or more TSVs from a field of TSVs in at least one IC device, and coupling each selected TSV to at least one of a test input and a test evaluation circuit.
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公开(公告)号：US20170178713A1
公开(公告)日：2017-06-22
申请号：US15391295
申请日：2016-12-27
Applicant: Rambus Inc.
Inventor： Richard Perego , Thomas Vogelsang , John Brooks
IPC: G11C11/406 , G11C11/408
CPC classification number: G11C11/406 , G11C11/40603 , G11C11/40611 , G11C11/40618 , G11C11/408 , G11C2211/4061
Abstract: The present disclosure describes DRAM architectures and refresh controllers that allow for scheduling of an opportunistic refresh of a DRAM device concurrently with normal row activate command directed toward the DRAM device. Each activate command affords an “opportunity” to refresh another independent row (i.e., a wordline) within a memory device with no scheduling conflict.
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公开(公告)号：US09667898B2
公开(公告)日：2017-05-30
申请号：US14433003
申请日：2013-09-30
Applicant: Rambus Inc.
Inventor： Thomas Vogelsang , Michael Guidash , Song Xue
CPC classification number: H04N5/378 , H04N5/3355 , H04N5/35536 , H04N5/35545 , H04N5/37455 , H04N5/3765
Abstract: An image sensor architecture with multi-bit sampling is implemented within an image sensor system. A pixel signal produced in response to light incident upon a photosensitive element is converted to a multiple-bit digital value representative of the pixel signal. If the pixel signal exceeds a sampling threshold, the photosensitive element is reset. During an image capture period, digital values associated with pixel signals that exceed a sampling threshold are accumulated into image data.
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