公开(公告)号：US06963967B1

公开(公告)日：2005-11-08

申请号：US09588508

申请日：2000-06-06

申请人： Guy Lynn Guthrie ,  Ravi Kumar Arimilli ,  John Steven Dodson ,  Derek Edward Williams

发明人： Guy Lynn Guthrie ,  Ravi Kumar Arimilli ,  John Steven Dodson ,  Derek Edward Williams

IPC分类号： G06F9/00 ,  G06F9/30 ,  G06F9/38

CPC分类号： G06F9/3851 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/383 ,  G06F9/3834 ,  G06F9/3842 ,  G06F9/3861

摘要： Disclosed is a method of processing instructions in a data processing system. An instruction sequence that includes a memory access instruction is received at a processor in program order. In response to receipt of the memory access instruction a memory access request and a barrier operation are created. The barrier operation is placed on an interconnect after the memory access request is issued to a memory system. After the barrier operation has completed, the memory access request is completed in program order. When the memory access request is a load request, the load request is speculatively issued if a barrier operation is pending. Data returned by the speculatively issued load request is only returned to a register or execution unit of the processor when an acknowledgment is received for the barrier operation.

摘要翻译： 公开了一种在数据处理系统中处理指令的方法。 包括存储器访问指令的指令序列以处理器的顺序被接收。 响应于接收到存储器访问指令，创建存储器访问请求和屏障操作。 在将存储器访问请求发布到存储器系统之后，屏障操作被放置在互连上。 屏障操作完成后，按程序顺序完成内存访问请求。 当存储器访问请求是加载请求时，如果屏障操作正在等待，则推测性地发出加载请求。 当接收到用于屏障操作的确认时，由推测发出的加载请求返回的数据仅返回到处理器的寄存器或执行单元。

公开(公告)号：US06785774B2

公开(公告)日：2004-08-31

申请号：US09978362

申请日：2001-10-16

申请人： Ravi Kumar Arimilli ,  Guy Lynn Guthrie ,  William J. Starke ,  Derek Edward Williams

发明人： Ravi Kumar Arimilli ,  Guy Lynn Guthrie ,  William J. Starke ,  Derek Edward Williams

IPC分类号： G06F1200

CPC分类号： G06F12/0831

摘要： A multiprocessor data processing system comprising a plurality of processing units, a plurality of caches, that is each affiliated with one of the processing units, and processing logic that, responsive to a receipt of a first system bus response to a coherency operation, causes the requesting processor to execute operations utilizing super-coherent data. The data processing system further includes logic eventually returning to coherent operations with other processing units responsive to an occurrence of a pre-determined condition. The coherency protocol of the data processing system includes a first coherency state that indicates that modification of data within a shared cache line of a second cache of a second processor has been snooped on a system bus of the data processing system. When the cache line is in the first coherency state, subsequent requests for the cache line is issued as a Z1 read on a system bus and one of two responses are received. If the response to the Z1 read indicates that the first processor should utilize local data currently available within the cache line, the first coherency state is changed to a second coherency state that indicates to the first processor that subsequent request for the cache line should utilize the data within the local cache and not be issued to the system interconnect. Coherency state transitions to the second coherency state is completed via the coherency protocol of the data processing system. Super-coherent data is provided to the processor from the cache line of the local cache whenever the second coherency state is set for the cache line and a request is received.

摘要翻译： 一种多处理器数据处理系统，包括多个处理单元，多个高速缓存，每个高速缓存与每个处理单元中的一个相关联;以及处理逻辑，响应于对一致性操作的第一系统总线响应的接收，使得 请求处理器使用超相干数据执行操作。 数据处理系统还包括逻辑，其最终返回到响应于预定条件的发生的其他处理单元的相干操作。 数据处理系统的一致性协议包括第一相关性状态，其指示在数据处理系统的系统总线上已经窥探第二处理器的第二高速缓存的共享高速缓存行内的数据的修改。 当高速缓存行处于第一相关性状态时，在系统总线上作为Z1读取发出对高速缓存行的后续请求，并且接收到两个响应中的一个。 如果对Z1读取的响应指示第一处理器应利用高速缓存行内当前可用的本地数据，则将第一相关性状态改变为第二相关性状态，其向第一处理器指示对高速缓存行的后续请求应当利用 本地缓存内的数据，不发给系统互连。 通过数据处理系统的一致性协议完成一致性状态转换到第二相关性状态。 每当为高速缓存行设置第二相关性状态并接收到请求时，将超相干数据从本地高速缓存行提供给处理器。

公开(公告)号：US06609192B1

公开(公告)日：2003-08-19

申请号：US09588607

申请日：2000-06-06

申请人： Guy Lynn Guthrie ,  Ravi Kumar Arimilli ,  John Steven Dodson ,  Derek Edward Williams

发明人： Guy Lynn Guthrie ,  Ravi Kumar Arimilli ,  John Steven Dodson ,  Derek Edward Williams

IPC分类号： G06F9312

CPC分类号： G06F9/30087 ,  G06F9/3834 ,  G06F9/3842

摘要： Disclosed is a multiprocessor data processing system that executes loads transactions out of order with respect to a barrier operation. The data processing system includes a memory and a plurality of processors coupled to an interconnect. At least one of the processors includes an instruction sequencing unit for fetching an instruction sequence in program order for execution. The instruction sequence includes a first and a second load instruction and a barrier instruction, which is between the first and second load instructions in the instruction sequence. Also included in the processor is a load/store unit (LSU), which has a load request queue (LRQ) that temporarily buffers load requests associated with the first and second load instructions. The LRQ is coupled to a load request arbitration unit, which selects an order of issuing the load requests from the LRQ. Then a controller issues a load request associated with the second load instruction to memory before completion of a barrier operation associated with the barrier instruction. Alternatively, load requests are issued out-of-order with respect to the program order before or after the barrier instruction. The load request arbitration unit selects the request associated with the second load instruction before a request associated with the first load instruction, and the controller issues the request associated with the second load instruction before the request associated with the first load instruction and before issuing the barrier operation.

摘要翻译： 公开了一种多处理器数据处理系统，其针对屏障操作执行无序的负载事务。 数据处理系统包括存储器和耦合到互连的多个处理器。 至少一个处理器包括用于以程序顺序取出指令序列以执行的指令排序单元。 指令序列包括在指令序列中的第一和第二加载指令之间的第一和第二加载指令和障碍指令。 还包括在处理器中的是装载/存储单元（LSU），其具有临时缓冲与第一和第二加载指令相关联的加载请求的加载请求队列（LRQ）。 LRQ耦合到负载请求仲裁单元，该单元从LRQ中选择发出负载请求的顺序。 然后，在与障碍指令相关联的屏障操作完成之前，控制器向存储器发出与第二加载指令相关联的加载请求。 或者，负载请求在屏障指令之前或之后相对于程序顺序发出无序。 负载请求仲裁单元在与第一加载指令相关联的请求之前选择与第二加载指令相关联的请求，并且控制器在与第一加载指令相关联的请求之前发布与第二加载指令相关联的请求，并且在发布屏障之前 操作。

公开(公告)号：US06292908B1

公开(公告)日：2001-09-18

申请号：US09175391

申请日：1998-10-19

申请人： Ravi Kumar Arimilli ,  Keenan Wynn Franz ,  David B. Shuler ,  Derek Edward Williams

发明人： Ravi Kumar Arimilli ,  Keenan Wynn Franz ,  David B. Shuler ,  Derek Edward Williams

IPC分类号： G06F1130

CPC分类号： G06F11/364 ,  G06F11/349

摘要： An apparatus and method for monitoring an internal communication path, i.e. an internal bus, of an integrated circuit is described. The internal bus operates at a particular frequency, fb. An image of the internal bus is produced, operating at a lower frequency of operations, fo, which is more amenable to monitoring by test equipment. Signals are received from and driven to the bus using driver/receiver circuitry. The signals may be input-only, output-only, or bi-directional signals. The signals to be monitored are tapped in the driver/receiver circuitry. Depending on the placement of the signal taps in the driver/receiver logic, the signals may be “out-of-phase” with respect to one another. A buffer/align unit processes the signals in order to produce a time delayed version of the signals. The buffer/aliqn unit is used to bring each of the monitored signals back in phase relative to one another. Encoding circuitry encodes the time delayed version of the bus in a manner that produces an image of the bus at the lower frequency of operations, fo. The encoding circuitry considers the values of the monitored signals over an encoding window, and produces an encoded value for each signal at the lower frequency of operations, fo.

摘要翻译： 描述了用于监视集成电路的内部通信路径即内部总线的装置和方法。 内部总线以特定频率fb运行。 生产内部总线的图像，操作频率较低，更适合于测试设备的监控。 使用驱动器/接收器电路从信号接收和驱动到总线。 信号可以是仅输入信号，仅输出信号或双向信号。 要监视的信号被点击在驱动器/接收器电路中。 根据驱动器/接收器逻辑中的信号抽头的布置，信号可能相对于彼此“异相”。 缓冲器/对准单元处理信号以产生信号的时间延迟版本。 缓冲器/ aliqn单元用于使每个被监控的信号相对于彼此反相。 编码电路以以更低的操作频率fo产生总线的图像的方式对总线的时间延迟版本进行编码。 编码电路在编码窗口中考虑监视信号的值，并且以较低的操作频率fo产生每个信号的编码值。

公开(公告)号：US06175930B1

公开(公告)日：2001-01-16

申请号：US09024586

申请日：1998-02-17

申请人： Ravi Kumar Arimilli ,  John Steven Dodson ,  Derek Edward Williams ,  Jerry Don Lewis

发明人： Ravi Kumar Arimilli ,  John Steven Dodson ,  Derek Edward Williams ,  Jerry Don Lewis

IPC分类号： H02H305

CPC分类号： G06F12/0831

摘要： A register associated with the architected logic queue of a memory-coherent device within a multiprocessor system contains a flag set whenever an architected operation—one which might affect the storage hierarchy as perceived by other devices within the system—is posted in the snoop queue of a remote snooping device. The flag remains set and is reset only when a synchronization instruction (such as the “sync” instruction supported by the PowerPC™ family of devices) is received from a local processor. The state of the flag thus provides historical information regarding architected operations which may be pending in other devices within the system after being snooped from the system bus. This historical information is utilized to determine whether a synchronization operation should be presented on the system bus, allowing unnecessary synchronization operations to be filtered and additional system bus cycles made available for other purposes. When a local processor issues a synchronization instruction to the device managing the architected logic queue, the instruction is generally accepted when the architected logic queue is empty. Otherwise the architected operation is retried back to the local processor until the architected logic queue becomes empty. If the flag is set when the synchronization instruction is accepted from the local processor, it is presented on the system bus. If the flag is not set when the synchronization instruction is received from the local processor, the synchronization operation is unnecessary and is not presented on the system bus.

摘要翻译： 与多处理器系统中的存储器相干设备的架构化逻辑队列相关联的寄存器包含标志集，每当可以影响系统内其他设备感知到的存储层次结构的操作（一个可能影响系统中的其他设备的架构操作）被发布在 一个远程监听设备。 该标志保持置位，并且仅当从本地处理器接收到同步指令（例如由PowerPC TM系列器件支持的“sync”指令）时才会复位该标志。 因此，标志的状态提供关于在从系统总线窥探之后可能在系统内的其他设备中挂起的架构操作的历史信息。 该历史信息用于确定是否应在系统总线上呈现同步操作，从而允许滤除不必要的同步操作，并为其他目的提供额外的系统总线周期。 当本地处理器向管理架构的逻辑队列的设备发出同步指令时，当架构的逻辑队列为空时，通常会接受该指令。 否则，架构操作将重新回到本地处理器，直到架构化的逻辑队列变为空。 如果在本地处理器接受同步指令时设置了标志，则会将其显示在系统总线上。 如果当从本地处理器接收到同步指令时未设置标志，则不需要同步操作，并且不会在系统总线上呈现同步操作。

公开(公告)号：US6092132A

公开(公告)日：2000-07-18

申请号：US175612

申请日：1998-10-19

申请人： Ravi Kumar Arimilli ,  Keenan Wynn Franz ,  David B. Shuler ,  Derek Edward Williams

发明人： Ravi Kumar Arimilli ,  Keenan Wynn Franz ,  David B. Shuler ,  Derek Edward Williams

IPC分类号： G06F13/42 ,  G06F13/00

CPC分类号： G06F13/4213

摘要： An apparatus and method for monitoring a PowerPC 60x bus within an integrated circuit is described. The 60x bus operates at a particular frequency, f.sub.b. An image of the 60x bus is produced, operating at a lower frequency of operations, f.sub.o, which is more amenable to monitoring by test equipment. Signals are received from and driven to the bus using driver/receiver circuitry. The signals may be input-only, output-only, or bi-directional signals. The signals to be monitored are tapped in the driver/receiver circuitry. Masking circuitry within the driver/receiver circuitry masks bi-directional signals, such as ARTRY.sub.-- and SHD.sub.--, during the pre-charge cycles, when these bi-directional signals are in an unpredictable state. Depending on the placement of the signal taps in the driver/receiver logic, the signals may be "out-of-phase" with respect to one another. A buffer/align unit is used to bring each of the monitored signals back in phase relative to one another. Encoding circuitry encodes the time delayed version of the bus in a manner that produces an image of the bus at the lower frequency of operations, f.sub.o. The encoding circuitry considers the values of the monitored signals over an encoding window, and produces an encoded value for each signal at the lower frequency of operations, f.sub.o.

摘要翻译： 描述了用于监视集成电路内的PowerPC 60x总线的装置和方法。 60x总线以特定频率fb运行。 生产60x总线的图像，操作频率较低，更适合于测试设备的监控。 使用驱动器/接收器电路从信号接收和驱动到总线。 信号可以是仅输入信号，仅输出信号或双向信号。 要监视的信号被点击在驱动器/接收器电路中。 当这些双向信号处于不可预测状态时，驱动器/接收器电路内的屏蔽电路在预充电周期期间屏蔽双向信号，例如ARTRY-和SHD-。 根据驱动器/接收器逻辑中的信号抽头的布置，信号可能相对于彼此“异相”。 使用缓冲器/对准单元使每个被监视的信号相对于彼此同相。 编码电路以以更低的操作频率fo产生总线的图像的方式对总线的时间延迟版本进行编码。 编码电路在编码窗口中考虑监视信号的值，并且以较低的操作频率fo产生每个信号的编码值。

公开(公告)号：US6061762A

公开(公告)日：2000-05-09

申请号：US839442

申请日：1997-04-14

申请人： Ravi Kumar Arimilli ,  John Steven Dodson ,  Jerry Don Lewis ,  Derek Edward Williams

发明人： Ravi Kumar Arimilli ,  John Steven Dodson ,  Jerry Don Lewis ,  Derek Edward Williams

IPC分类号： G06F12/08 ,  G06F12/00 ,  G06F13/00

CPC分类号： G06F12/0802

摘要： Cache and architectural specific functions are layered within a controller, simplifying design requirements. Faster performance may be achieved and individual segments of the overall design may be individually tested and formally verified. Transition between memory consistency models is also facilitated. Different segments of the overall design may be implemented in distinct integrated circuits, allowing less expensive processes to be employed where suitable.

摘要翻译： 缓存和架构特定功能在控制器内分层，简化了设计要求。 可以实现更快的性能，并且可以单独测试和正式验证整体设计的各个部分。 内存一致性模型之间的转换也是有利的。 总体设计的不同部分可以在不同的集成电路中实现，从而允许在合适的情况下采用较便宜的工艺。

公开(公告)号：US5931924A

公开(公告)日：1999-08-03

申请号：US839437

申请日：1997-04-14

申请人： Ravi Kumar Arimilli ,  John Steven Dodson ,  Jerry Don Lewis ,  Derek Edward Williams

发明人： Ravi Kumar Arimilli ,  John Steven Dodson ,  Jerry Don Lewis ,  Derek Edward Williams

IPC分类号： G06F15/16 ,  G06F13/364 ,  G06F15/177 ,  G06F13/14

CPC分类号： G06F13/364

摘要： A method and system for controlling access to a shared resource in a data processing system are described. According to the method, a number of requests for access to the resource are generated by a number of requesters that share the resource. Each of the requesters is associated with a priority weight that indicates a probability that the associated requester will be assigned a highest current priority. Each requester is then assigned a current priority that is determined substantially randomly with respect to previous priorities of the requesters. In response to the current priorities of the requesters, a request for access to the resource is granted. In one embodiment, a requester corresponding to a granted request is signaled that its request has been granted, and a requester corresponding to a rejected request is signaled that its request was not granted.

摘要翻译： 描述了用于控制对数据处理系统中的共享资源的访问的方法和系统。 根据该方法，通过共享资源的多个请求者生成对资源的访问的多个请求。 每个请求者与优先级权重相关联，该权重指示相关请求者将被分配最高当前优先级的概率。 然后分配每个请求者相对于请求者的先前优先级基本随机确定的当前优先级。 为响应请求者的当前优先级，授予访问资源的请求。 在一个实施例中，与被许可的请求相对应的请求者用信号通知其请求已经被许可，并且与被拒绝的请求相对应的请求者用信号通知其请求未被授予。

公开(公告)号：US07213248B2

公开(公告)日：2007-05-01

申请号：US10268729

申请日：2002-10-10

申请人： Ravi Kumar Arimilli ,  Derek Edward Williams

发明人： Ravi Kumar Arimilli ,  Derek Edward Williams

IPC分类号： G06F9/46 ,  G06F12/14 ,  G06F15/00

CPC分类号： G06F9/52 ,  G06F9/3004 ,  G06F9/30072 ,  G06F9/30087

摘要： A multiprocessor data processing system includes a plurality of processors coupled to an interconnect and to a global promotion facility containing at least one promotion bit field. A first processor executes a high speed instruction sequence including a load-type instruction to acquire a promotion bit field within the global promotion facility exclusive of at least a second processor. The request may be made visible to all processors coupled to the interconnect. In response to execution of the load-type instruction, a register of the first processor receives a register bit field indicating whether or not the promotion bit field was acquired by execution of the load-type instruction. While the first processor holds the promotion bit field exclusive of the second processor, the second processor is permitted to initiate a request on the interconnect. Advantageously, promotion bit fields are handled separately from data, and the communication of promotion bit fields does not entail the movement of data cache lines.

摘要翻译： 多处理器数据处理系统包括耦合到互连的多个处理器和包含至少一个促销位字段的全局推广设备。 第一处理器执行包括负载型指令的高速指令序列，以在除了至少第二处理器之外的全局促进设备中获取促销位字段。 所述请求可以被耦合到互连的所有处理器可见。 响应于负载型指令的执行，第一处理器的寄存器接收指示通过执行负载型指令是否获取了促销位字段的寄存器位字段。 虽然第一处理器保持不属于第二处理器的升级位字段，但允许第二处理器在互连上发起请求。 优选地，促销比特字段与数据分开处理，并且促销比特字段的通信不需要数据高速缓存行的移动。

公开(公告)号：US06925551B2

公开(公告)日：2005-08-02

申请号：US10268742

申请日：2002-10-10

申请人： Ravi Kumar Arimilli ,  Derek Edward Williams

发明人： Ravi Kumar Arimilli ,  Derek Edward Williams

IPC分类号： G06F9/30 ,  G06F9/32 ,  G06F12/00 ,  G06F12/08 ,  G06F12/14 ,  G06F13/14 ,  G06F15/163

CPC分类号： G06F12/0831 ,  G06F9/3004 ,  G06F9/30054 ,  G06F9/30072 ,  G06F9/30087

摘要： A multiprocessor data processing system includes first and second processors coupled to an interconnect and to a global promotion facility containing at least one promotion bit field. The first processor initiates execution of a branch-type instruction to request acquisition of a promotion bit field exclusive of at least the second processor. In response to the branch-type instruction, the first processor issues an access request to acquire the promotion bit field. After the accessing request, a register of the first processor receives a register bit indicating whether or not the promotion bit field was successfully acquired by the access request. As a part of executing the branch-type instruction, the first processor selects among a first execution path and a second execution path in response to the register bit.

摘要翻译： 多处理器数据处理系统包括耦合到互连的第一和第二处理器以及包含至少一个促销位字段的全局推广设备。 第一处理器启动分支型指令的执行，以请求获取除了至少第二处理器之外的促销位字段。 响应于分支型指令，第一处理器发出获取促销位字段的访问请求。 在访问请求之后，第一处理器的寄存器接收指示是否通过访问请求成功获取了促销位字段的寄存器位。 作为执行分支型指令的一部分，第一处理器响应于寄存器位在第一执行路径和第二执行路径之中进行选择。