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    Method of manufacturing semiconductor device
    11.
    发明授权
    Method of manufacturing semiconductor device 有权
    制造半导体器件的方法

    公开(公告)号：US09508554B2

    公开(公告)日：2016-11-29

    申请号：US14869988

    申请日：2015-09-29

    Applicant: Renesas Electronics Corporation

    Inventor： Kazuharu Yamabe ,  Shinichiro Abe ,  Shoji Yoshida ,  Hideaki Yamakoshi ,  Toshio Kudo ,  Seiji Muranaka ,  Fukuo Owada ,  Daisuke Okada

    IPC: H01L21/4763 ,  H01L21/28 ,  H01L29/66 ,  H01L29/792

    CPC classification number: H01L21/28282 ,  H01L21/28194 ,  H01L29/66833 ,  H01L29/792

    Abstract: To provide a semiconductor device having improved performance while improving the throughput in the manufacturing steps of the semiconductor device. An insulating film portion comprised of first, second, third, fourth, and fifth insulating films is formed on a semiconductor substrate. The second insulating film is a first charge storage film and the fourth insulating film is a second charge storage film. The first charge storage film contains silicon and nitrogen; the third insulating film contains silicon and oxygen; and the second charge storage film contains silicon and nitrogen. The thickness of the third insulating film is smaller than that of the first charge storage film and the thickness of the second charge storage film is greater than that of the first charge storage film. The third insulating film is formed by treating the upper surface of the first charge storage film with a water-containing treatment liquid.

    Abstract translation: 提供具有改进性能的半导体器件，同时提高半导体器件的制造步骤中的吞吐量。 在半导体衬底上形成由第一，第二，第三，第四和第五绝缘膜构成的绝缘膜部分。 第二绝缘膜是第一电荷存储膜，第四绝缘膜是第二电荷存储膜。 第一电荷储存膜含有硅和氮; 第三绝缘膜含有硅和氧; 并且第二电荷储存膜含有硅和氮。 第三绝缘膜的厚度小于第一电荷存储膜的厚度，并且第二电荷存储膜的厚度大于第一电荷存储膜的厚度。 第三绝缘膜通过用含水处理液处理第一电荷存储膜的上表面而形成。

    SEMICONDUCTOR DEVICE
    13.
    发明申请
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20160071858A1

    公开(公告)日：2016-03-10

    申请号：US14942142

    申请日：2015-11-16

    Applicant: Renesas Electronics Corporation

    Inventor： Hideaki Yamakoshi ,  Daisuke Okada

    IPC: H01L27/115 ,  H01L29/423

    CPC classification number: H01L27/11524 ,  G11C16/0433 ,  G11C16/0441 ,  G11C16/10 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11531 ,  H01L29/42324 ,  H01L29/42328

    Abstract: Provided is a semiconductor device having improved performance. The semiconductor device includes the memory cells of a flash memory. Each of the memory cells includes a capacitor element for writing/erasing data having a gate electrode formed of a part of a floating gate electrode, and a MISFET for reading data having a gate electrode formed of another part of the floating gate electrode. The capacitor element for writing/erasing data has a p-type semiconductor region and an n-type semiconductor region which have opposite conductivity types. The length of the floating gate electrode in a gate length direction in the capacitor element for writing/erasing data is smaller than the length of the floating gate electrode in the gate length direction in the MISFET for reading data.

    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME
    14.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME 有权
    半导体器件及其制造方法

    公开(公告)号：US20150145023A1

    公开(公告)日：2015-05-28

    申请号：US14548595

    申请日：2014-11-20

    Applicant: Renesas Electronics Corporation

    Inventor： Tsuyoshi Arigane ,  Daisuke Okada ,  Digh Hisamoto

    IPC: H01L27/115 ,  H01L29/423 ,  H01L21/28 ,  H01L29/51

    CPC classification number: H01L29/66833 ,  H01L21/2815 ,  H01L21/28158 ,  H01L21/28282 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/42344 ,  H01L29/42364 ,  H01L29/511 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/792

    Abstract: To provide a semiconductor device having a nonvolatile memory improved in characteristics. In the semiconductor device, a nonvolatile memory has a high-k insulating film (high dielectric constant film) between a control gate electrode portion and a memory gate electrode portion and a transistor of a peripheral circuit region has a high-k/metal configuration. The high-k insulating film arranged between the control gate electrode portion and the memory gate electrode portion relaxes an electric field intensity at the end portion (corner portion) of the memory gate electrode portion on the side of the control gate electrode portion. This results in reduction in uneven distribution of charges in a charge accumulation portion (silicon nitride film) and improvement in erase accuracy.

    Abstract translation: 提供具有改善特性的非易失性存储器的半导体器件。 在半导体器件中，非易失性存储器在控制栅电极部分和存储栅电极部分之间具有高k绝缘膜（高介电常数膜），并且外围电路区域的晶体管具有高k /金属构造。 布置在控制栅电极部分和存储栅电极部分之间的高k绝缘膜松弛在控制栅电极部分一侧的存储栅电极部分的端部（拐角部分）的电场强度。 这导致电荷累积部分（氮化硅膜）中电荷的不均匀分布的减少和擦除精度的提高。

    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
    16.
    发明申请
    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 审中-公开
    半导体器件及其制造方法

    公开(公告)号：US20140008716A1

    公开(公告)日：2014-01-09

    申请号：US13931874

    申请日：2013-06-29

    Applicant: Renesas Electronics Corporation

    Inventor： Tsuyoshi Arigane ,  Digh Hisamoto ,  Yutaka Okuyama ,  Takashi Hashimoto ,  Daisuke Okada

    IPC: H01L29/792 ,  H01L29/66

    CPC classification number: H01L29/792 ,  H01L21/823481 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/42344 ,  H01L29/66833

    Abstract: When the width of an isolation region is reduced through the scaling of a memory cell to reduce the distance between the memory cell and an adjacent memory cell, the electrons or holes injected into the charge storage film of the memory cell are diffused into the portion of the charge storage film located over the isolation region to interfere with each other and possibly impair the reliability of the memory cell. In a semiconductor device, the charge storage film of the memory cell extends to the isolation region located between the adjacent memory cells. The effective length of the charge storage film in the isolation region is larger than the width of the isolation region. Here, the effective length indicates the length of the region of the charge storage film which is located over the isolation region and in which charges are not stored.

    Abstract translation: 当通过存储单元的缩放来减小隔离区域的宽度以减小存储单元和相邻存储单元之间的距离时，注入到存储单元的电荷存储膜中的电子或空穴被扩散到 位于隔离区域上方的电荷存储膜彼此干涉并可能损害存储单元的可靠性。 在半导体器件中，存储单元的电荷存储膜延伸到位于相邻存储单元之间的隔离区域。 隔离区域中的电荷存储膜的有效长度大于隔离区域的宽度。 这里，有效长度表示位于隔离区上方的电荷存储膜的区域的长度，其中不存储电荷。

    Semiconductor device and method of driving semiconductor device
    18.
    发明授权
    Semiconductor device and method of driving semiconductor device 有权

    公开(公告)号：US09558826B2

    公开(公告)日：2017-01-31

    申请号：US15152391

    申请日：2016-05-11

    Applicant: Renesas Electronics Corporation

    Inventor： Tsuyoshi Arigane ,  Daisuke Okada ,  Digh Hisamoto

    IPC: G11C16/04 ,  G11C16/14 ,  H01L29/423 ,  H01L27/115 ,  H01L29/51 ,  G11C16/34

    Abstract: A first potential and a second potential lower than the first potential are applied to a first end of a memory gate electrode part of the nonvolatile memory and to a second end of the memory gate electrode part, respectively, so that a current is caused to flow in a direction in which the memory gate electrode part extends, then, a hole is injected from the memory gate electrode part into a charge accumulating part below it, therefore, an electron accumulated in the charge accumulating part is eliminated. By causing the current to flow through the memory gate electrode part of a memory cell region as described above, Joule heat can be generated to heat the memory cell. Consequently, in the erasing by a FN tunneling method in which the erasing characteristics degrade at a low temperature, the erasing speed can be improved by heating the memory gate electrode part.

    Semiconductor device
    20.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US09196363B2

    公开(公告)日：2015-11-24

    申请号：US14584533

    申请日：2014-12-29

    Applicant: Renesas Electronics Corporation

    Inventor： Hideaki Yamakoshi ,  Daisuke Okada

    IPC: G11C16/04 ,  H01L27/115 ,  G11C16/10

    CPC classification number: H01L27/11524 ,  G11C16/0433 ,  G11C16/0441 ,  G11C16/10 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11531 ,  H01L29/42324 ,  H01L29/42328

    Abstract: Provided is a semiconductor device having improved performance. The semiconductor device includes the memory cells of a flash memory. Each of the memory cells includes a capacitor element for writing/erasing data having a gate electrode formed of a part of a floating gate electrode, and a MISFET for reading data having a gate electrode formed of another part of the floating gate electrode. The capacitor element for writing/erasing data has a p-type semiconductor region and an n-type semiconductor region which have opposite conductivity types. The length of the floating gate electrode in a gate length direction in the capacitor element for writing/erasing data is smaller than the length of the floating gate electrode in the gate length direction in the MISFET for reading data.

    Abstract translation: 提供了具有改进的性能的半导体器件。 半导体器件包括闪速存储器的存储单元。 每个存储单元包括用于写入/擦除具有由浮置栅电极的一部分形成的栅电极的数据的电容器元件和用于读取具有由浮置栅电极的另一部分形成的栅电极的数据的MISFET。 用于写入/擦除数据的电容器元件具有具有相反导电类型的p型半导体区域和n型半导体区域。 用于写入/擦除数据的电容器元件中的栅极长度方向上的浮栅电极的长度小于用于读取数据的MISFET中的栅极长度方向上的浮栅电极的长度。

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