公开(公告)号：US20170256634A1

公开(公告)日：2017-09-07

申请号：US15390491

申请日：2016-12-24

Applicant: Renesas Electronics Corporation

Inventor： Hitoshi MATSUURA

IPC: H01L29/739 ,  H01L29/10 ,  H01L29/423 ,  H01L29/06

CPC classification number: H01L29/7397 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/4238 ,  H01L29/66325

Abstract: A linear active cell region is formed from a plurality of divided active cell regions arranged apart from each other in a second direction (y direction). The linear hole collector cell region is formed from a plurality of divided hole collector cell regions arranged apart from each other in the second direction (y direction). A P-type floating region is formed in a semiconductor substrate between the linear active cell region and the linear hole collector cell region adjacent to each other in a first direction (x direction), between the divided active cell regions adjacent to each other in the second direction (y direction), and between the divided hole collector cell regions adjacent to each other in the second direction (y direction).

公开(公告)号：US20170054011A1

公开(公告)日：2017-02-23

申请号：US15181024

申请日：2016-06-13

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hitoshi MATSUURA

IPC: H01L29/739 ,  H01L21/768 ,  H01L23/535 ,  H01L29/10 ,  H01L29/66

CPC classification number: H01L29/7397 ,  H01L21/76895 ,  H01L23/535 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/1004 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/407 ,  H01L29/41725 ,  H01L29/4236 ,  H01L29/66348

Abstract: The surface of an interlayer insulating film formed over an emitter coupling portion and the surface of an emitter electrode formed over the interlayer insulating film are caused to have a gentle shape, in particular, at the end of the emitter coupling portion, by forming the emitter coupling portion over a main surface of a semiconductor substrate and integrally with trench gate electrodes in order to form a spacer over the sidewall of the emitter coupling portion. Thereby, stress is dispersed, not concentrated in an acute angle portion of the emitter coupling portion when an emitter wire is coupled to the emitter electrode (emitter pad), and hence occurrence of a crack can be suppressed. Further, by forming the spacer, the concavities and convexities to be formed in the surface of the emitter electrode can be reduced, whereby the adhesiveness between the emitter electrode and the emitter wire can be improved.

Abstract translation: 通过形成发射极耦合部分的发射极耦合部分上形成的层间绝缘膜的表面和形成在层间绝缘膜上的发射电极的表面，特别是在发射极耦合部分的末端，具有平缓的形状 耦合部分在半导体衬底的主表面上并与沟槽栅极电极整体形成以在发射极耦合部分的侧壁上形成间隔物。 因此，当发射极线耦合到发射极（发射极焊盘）时，应力分散而不集中在发射极耦合部分的锐角部分中，因此可以抑制裂纹的发生。 此外，通过形成间隔物，可以减少在发射电极的表面中形成的凹凸，从而可以提高发射极和发射极线之间的粘附性。

公开(公告)号：US20170033206A1

公开(公告)日：2017-02-02

申请号：US15171634

申请日：2016-06-02

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hitoshi MATSUURA

IPC: H01L29/739 ,  H01L29/40 ,  H01L29/10 ,  H01L29/06

CPC classification number: H01L29/7397 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/404 ,  H01L29/407 ,  H01L29/4238

Abstract: The performance of a semiconductor device is improved. An emitter electrode is coupled to a P-type body region and an N+-type emitter region of a linear active cell region via a contact groove formed on an interlayer insulating film and is coupled to a P-type body region of a linear hole connector cell region via a contact groove. The contact grooves arranged in the linear hole connector cell region are shorter than the contact groove in plan view.

Abstract translation: 提高了半导体器件的性能。 发射电极经由形成在层间绝缘膜上的接触槽与P型体区域和线性有源电极区域的N +型发射极区域耦合，并连接到线性孔连接器的P型体区域 电池区域。 布置在直孔连接孔单元区域中的接触槽在平面图中比接触槽短。

公开(公告)号：US20160351703A1

公开(公告)日：2016-12-01

申请号：US15236678

申请日：2016-08-15

Applicant: Renesas Electronics Corporation

Inventor： Hitoshi MATSUURA ,  Yoshito Nakazawa

IPC: H01L29/78 ,  H01L29/49 ,  H01L29/06 ,  H01L29/40

CPC classification number: H01L29/7813 ,  H01L29/0619 ,  H01L29/407 ,  H01L29/4983 ,  H01L29/78

Abstract: In characteristic test measurements of double-gate-in-trench p-channel power MOSFETs each having a p+ polysilicon gate electrode and a p+ field plate electrode in a trench, which were fabricated according to common design techniques, it has been found that, under conditions where a negative gate bias is applied continuously at high temperature with respect to the substrate, an absolute value of threshold voltage tends to increase steeply after the lapse of a certain period of stress application time. To solve this problem, the present invention provides a p-channel power MOSFET having an n-type polysilicon linear field plate electrode and an n-type polysilicon linear gate electrode in each trench part thereof.

Abstract translation: 在沟槽中具有p +多晶硅栅电极和p +场板电极的双栅沟槽p沟道功率MOSFET的特性测试测量中，根据常规设计技术制造，已经发现， 在高温下相对于衬底连续施加负栅极偏压的条件下，阈值电压的绝对值在经过一定的压力施加时间之后倾向于急剧增加。 为了解决这个问题，本发明提供一种在其每个沟槽部分中具有n型多​​晶硅线性场极板电极和n型多晶硅线性栅极电极的p沟道功率MOSFET。

公开(公告)号：US20160240643A1

公开(公告)日：2016-08-18

申请号：US15138687

申请日：2016-04-26

Applicant: Renesas Electronics Corporation

Inventor： Hitoshi MATSUURA

IPC: H01L29/739 ,  H01L29/66 ,  H01L29/06 ,  H01L29/40 ,  H01L29/08 ,  H01L29/10

CPC classification number: H01L29/7397 ,  H01L29/0619 ,  H01L29/0638 ,  H01L29/0696 ,  H01L29/0804 ,  H01L29/0821 ,  H01L29/1095 ,  H01L29/36 ,  H01L29/404 ,  H01L29/407 ,  H01L29/41708 ,  H01L29/4236 ,  H01L29/42364 ,  H01L29/42368 ,  H01L29/66333 ,  H01L29/66348 ,  H01L29/7393 ,  H01L29/7395 ,  H01L29/7813

Abstract: A switching loss is prevented from being deteriorated by suppressing increase in a gate capacitance due to a cell shrink of an IE type trench gate IGBT. A cell formation region is configured of a linear active cell region, a linear hole collector cell region, and a linear inactive cell region between them. Then, upper surfaces of the third and fourth linear trench gate electrodes which are formed so as to sandwich both sides of the linear hole collector cell region and electrically connected to an emitter electrode are positioned to be lower than upper surfaces of the first and second linear trench gate electrodes which are formed so as to sandwich both sides of the linear active cell region and electrically connected to a gate electrode.

公开(公告)号：US20150236144A1

公开(公告)日：2015-08-20

申请号：US14705035

申请日：2015-05-06

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hitoshi MATSUURA

IPC: H01L29/739 ,  H01L29/08 ,  H01L29/417 ,  H01L29/10 ,  H01L29/06

CPC classification number: H01L29/7397 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/0804 ,  H01L29/0821 ,  H01L29/0865 ,  H01L29/0882 ,  H01L29/1095 ,  H01L29/404 ,  H01L29/407 ,  H01L29/41708 ,  H01L29/4236 ,  H01L29/66348 ,  H01L29/7395 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In a method of further enhancing the performance of a narrow active cell IE type trench gate IGBT having the width of active cells narrower than that of inactive cells, it is effective to shrink the cells so that the IE effects are enhanced. However, when the cells are shrunk simply, the switching speed is reduced due to increased gate capacitance. A cell formation area of the IE type trench gate IGBT is basically composed of first linear unit cell areas having linear active cell areas, second linear unit cell areas having linear hole collector areas and linear inactive cell areas disposed therebetween.

Abstract translation: 在进一步提高活性单元宽度比非活性单元窄的窄活性单元IE型沟槽栅极IGBT的性能的方法中，收缩单元是有效的，使得IE效应增强。 然而，当电池简单地收缩时，由于栅极电容增加，开关速度降低。 IE型沟槽栅极IGBT的单元形成区域基本上由具有线性有源单元区域的第一线性单元单元区域，具有线性空穴集电区域的第二线性单位单元区域和设置在其间的线性非活性单元区域组成。

公开(公告)号：US20130328105A1

公开(公告)日：2013-12-12

申请号：US13903068

申请日：2013-05-28

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hitoshi MATSUURA

IPC: H01L29/739 ,  H01L29/66

CPC classification number: H01L29/7397 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/0834 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/66348

Abstract: In an equal width active cell IE type IGBT, a wide active cell IE type IGBT, and the like, an active cell region is equal in trench width to an inactive cell region, or the trench width of the inactive cell region is narrower. Accordingly, it is relatively easy to ensure the breakdown voltage. However, with such a structure, an attempt to enhance the IE effect entails problems such as further complication of the structure. The present invention provides a narrow active cell IE type IGBT having an active cell two-dimensional thinned-out structure, and not having a substrate trench for contact.

Abstract translation: 在相等宽度的有源电池IE型IGBT，宽活性电池IE型IGBT等中，有源电池区域的沟槽宽度相当于非活性电池区域，或者非活性电池区域的沟槽宽度较窄。 因此，相对容易确保击穿电压。 然而，通过这样的结构，提高IE效应的尝试需要诸如结构进一步复杂化的问题。 本发明提供一种具有活性电池二维稀疏结构的窄活性电池IE型IGBT，并且不具有用于接触的衬底沟槽。

公开(公告)号：US20130187223A1

公开(公告)日：2013-07-25

申请号：US13792134

申请日：2013-03-10

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hitoshi MATSUURA ,  Yoshito NAKAZAWA ,  Tsuyoshi KACHI ,  Yuji YATSUDA

IPC: H01L29/78

CPC classification number: H01L27/0629 ,  H01L21/26586 ,  H01L21/76897 ,  H01L29/0615 ,  H01L29/086 ,  H01L29/1095 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7827 ,  H01L29/8725

Abstract: A gate trench 13 is formed in a semiconductor substrate 10. The gate trench 13 is provided with a gate electrode 16 formed over a gate insulating film 14. A portion of the gate electrode 16 protrudes from the semiconductor substrate 10, and a sidewall 24 is formed over a side wall portion of the protruding portion. A body trench 25 is formed in alignment with an adjacent gate electrode 16. A cobalt silicide film 28 is formed over a surface of the gate electrode 16 and over a surface of the body trench 25. A plug 34 is formed using an SAC technique.

公开(公告)号：US20250040162A1

公开(公告)日：2025-01-30

申请号：US18775122

申请日：2024-07-17

Applicant: Renesas Electronics Corporation

Inventor： Hitoshi MATSUURA

IPC: H01L29/739 ,  H01L29/10 ,  H01L29/66

Abstract: A semiconductor device including an IGBT with improved switching characteristics is provided. Inside trenches formed inside a semiconductor substrate of an active cell, a trench gate electrode and a trench emitter electrode are formed through a gate insulating film. An n-type hole barrier region is formed inside the semiconductor substrate located between the trenches. A p-type base region is formed inside the hole barrier region. An n-type emitter region is formed inside the base region. A p-type floating region is formed inside the semiconductor substrate of an inactive cell. A depth of the floating region is shallower than each depth of the trenches, and is deeper than a depth of the base region.

公开(公告)号：US20230420550A1

公开(公告)日：2023-12-28

申请号：US18179739

申请日：2023-03-07

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Seigo NAMIOKA ,  Hitoshi MATSUURA ,  Ryota KURODA

IPC: H01L29/739 ,  H01L29/06 ,  H01L29/10 ,  H01L29/417 ,  H01L29/66

CPC classification number: H01L29/7397 ,  H01L29/0696 ,  H01L29/66348 ,  H01L29/41708 ,  H01L29/6634 ,  H01L29/1095

Abstract: A semiconductor device includes a trench emitter electrode located at a boundary between one end of an active cell region and an inactive cell region, a trench gate electrode located at a boundary between the other end of the active cell region and the inactive cell region, an end trench gate electrode connected to one end of the trench gate electrode, and an end trench emitter electrode connected to one end of the trench emitter electrode. A hole barrier region of a first conductivity type is provided under a body region of a second conductivity type between the end trench gate electrode and the end trench emitter electrode in a plan view. A body region in the active cell region and a body region in the inactive cell region are connected to each other by a body region between the end trench gate electrode and the end trench emitter electrode.