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    Semiconductor Device and Manufacturing Method of the Same
    5.
    发明申请
    Semiconductor Device and Manufacturing Method of the Same 有权
    半导体器件及其制造方法

    公开(公告)号：US20140193968A1

    公开(公告)日：2014-07-10

    申请号：US14100462

    申请日：2013-12-09

    Applicant: Renesas Electronics Corporation

    Inventor： Yoshito Nakazawa ,  Yuji Yatsuda

    IPC: H01L21/28

    CPC classification number: H01L29/7808 ,  H01L21/28008 ,  H01L21/28556 ,  H01L27/0255 ,  H01L29/0696 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/456 ,  H01L29/4916 ,  H01L29/66484 ,  H01L29/66545 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7811 ,  H01L29/7813

    Abstract: A method for manufacturing a semiconductor device having a field-effect transistor, including forming a trench in a semiconductor substrate, forming a first insulating film in the trench, forming an intrinsic polycrystalline silicon film over the first insulating film, and introducing first conductive type impurities into the intrinsic polycrystalline silicon film to form a first conductive film. The first conductive film is etched to form a first gate electrode in the trench. Next, a second insulating film is formed in the trench above the first insulating film and the first gate electrode, anda first conductivity type doped polycrystalline silicon film, having higher impurity concentration than the first gate electrode is formed over the second insulating film. The doped polycrystalline silicon film, upper part of the trench ton form a second gate electrode.

    Abstract translation: 一种制造具有场效应晶体管的半导体器件的方法，包括在半导体衬底中形成沟槽，在沟槽中形成第一绝缘膜，在第一绝缘膜上形成本征多晶硅膜，并引入第一导电类型杂质 进入本征多晶硅膜以形成第一导电膜。 蚀刻第一导电膜以在沟槽中形成第一栅电极。 接下来，在第二绝缘膜上形成第二绝缘膜，该第二绝缘膜形成在第一绝缘膜和第一栅电极之上的沟槽中，并且在第二绝缘膜上形成杂质浓度高于第一栅电极的第一导电型掺杂多晶硅膜。 掺杂多晶硅膜，沟槽ton的上部形成第二栅电极。

    Semiconductor device
    6.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US10903354B2

    公开(公告)日：2021-01-26

    申请号：US16371989

    申请日：2019-04-01

    Applicant: RENESAS ELECTRONICS CORPORATION

    Inventor： Yoshito Nakazawa

    IPC: H01L29/78 ,  H01L29/10 ,  H01L29/40 ,  H01L29/66 ,  H01L29/04 ,  H01L29/06 ,  H01L29/417 ,  H01L29/739 ,  H01L29/861 ,  H01L21/265 ,  H01L27/085

    Abstract: A semiconductor device includes: a cell region provided in a main surface of a semiconductor substrate composed of a crystal plane (100); a field insulating film embedded in the semiconductor substrate; and an annular p-type well region surrounding the cell region. The p-type well region includes a first region extending in a direction, a second region extending in a direction, and a third region connecting the first region and the second region and having an arc shape in plan view. The field insulating film has an opening provided in the p-type well region and extending along the p-type well region in plan view. The opening includes a first opening extending in the direction in the first region and a second opening extending in the direction in the second region, and the first opening and the second opening are divided from each other in the third region.

    Semiconductor device
    8.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US09520318B2

    公开(公告)日：2016-12-13

    申请号：US14995996

    申请日：2016-01-14

    Applicant: Renesas Electronics Corporation

    Inventor： Satoshi Eguchi ,  Yoshito Nakazawa

    IPC: H01L21/761 ,  H01L21/265 ,  H01L29/66 ,  H01L21/04 ,  H01L29/16 ,  H01L29/861 ,  H01L29/78 ,  H01L29/165 ,  H01L29/06 ,  H01L29/739 ,  H01L29/10 ,  H01L29/08

    CPC classification number: H01L21/761 ,  H01L21/0415 ,  H01L21/26506 ,  H01L21/26513 ,  H01L29/0634 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/66068 ,  H01L29/66712 ,  H01L29/7395 ,  H01L29/7811 ,  H01L29/861

    Abstract: A method for manufacturing a semiconductor device including a cell region and a peripheral region formed outside the cell region, comprising the steps of (a) providing a semiconductor substrate including a first epitaxial layer of a first conductivity type formed over a main surface thereof, (b) doping a lower band gap impurity for making the band gap smaller than the band gap of the first epitaxial layer before doping into the first epitaxial layer in the cell region, and thereby forming a lower band gap region, (c) after the step (b), forming a plurality of first column regions of a second conductivity type which is the opposite conductivity type to the first conductivity type in such a manner as to be separated from one another in the first epitaxial layer extending from the cell region to the peripheral region, and (d) after the step (c), forming a second epitaxial layer.

    Abstract translation: 一种制造半导体器件的方法，该半导体器件包括形成在晶胞区外的单元区域和周边区域，包括以下步骤：（a）提供包括在其主表面上形成的第一导电类型的第一外延层的半导体衬底（ b）掺杂较低带隙杂质，以在掺杂到单元区域内的第一外延层之后使带隙小于第一外延层的带隙，从而形成较低带隙区域，（c）在步骤 （b）中，形成与第一导电类型相反的导电类型的多个第一导电类型的第一列区域，以便在从单元区域扩展到第一导电类型的第一外延层中彼此分离 周边区域，（d）在步骤（c）之后，形成第二外延层。

    P-CHANNEL POWER MOSFET
    9.
    发明申请
    P-CHANNEL POWER MOSFET 有权
    P沟道功率MOSFET

    公开(公告)号：US20160351703A1

    公开(公告)日：2016-12-01

    申请号：US15236678

    申请日：2016-08-15

    Applicant: Renesas Electronics Corporation

    Inventor： Hitoshi MATSUURA ,  Yoshito Nakazawa

    IPC: H01L29/78 ,  H01L29/49 ,  H01L29/06 ,  H01L29/40

    CPC classification number: H01L29/7813 ,  H01L29/0619 ,  H01L29/407 ,  H01L29/4983 ,  H01L29/78

    Abstract: In characteristic test measurements of double-gate-in-trench p-channel power MOSFETs each having a p+ polysilicon gate electrode and a p+ field plate electrode in a trench, which were fabricated according to common design techniques, it has been found that, under conditions where a negative gate bias is applied continuously at high temperature with respect to the substrate, an absolute value of threshold voltage tends to increase steeply after the lapse of a certain period of stress application time. To solve this problem, the present invention provides a p-channel power MOSFET having an n-type polysilicon linear field plate electrode and an n-type polysilicon linear gate electrode in each trench part thereof.

    Abstract translation: 在沟槽中具有p +多晶硅栅电极和p +场板电极的双栅沟槽p沟道功率MOSFET的特性测试测量中，根据常规设计技术制造，已经发现， 在高温下相对于衬底连续施加负栅极偏压的条件下，阈值电压的绝对值在经过一定的压力施加时间之后倾向于急剧增加。 为了解决这个问题，本发明提供一种在其每个沟槽部分中具有n型多​​晶硅线性场极板电极和n型多晶硅线性栅极电极的p沟道功率MOSFET。

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