中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

21 records (took 0.028 seconds)

    Method of manufacturing semiconductor device
    11.
    发明授权
    Method of manufacturing semiconductor device 有权

    公开(公告)号：US10483273B2

    公开(公告)日：2019-11-19

    申请号：US16012362

    申请日：2018-06-19

    Applicant: RENESAS ELECTRONICS CORPORATION

    Inventor： Hideaki Yamakoshi ,  Takashi Hashimoto ,  Shinichiro Abe ,  Yuto Omizu

    IPC: H01L27/108 ,  H01L27/11563 ,  H01L21/28 ,  H01L27/1157 ,  H01L27/11573

    Abstract: A semiconductor device is obtained in which a first insulating film for a gate insulating film of a memory element is formed over a semiconductor substrate in a memory region, a second insulating film for a gate insulating film of a lower-breakdown-voltage MISFET is formed over the semiconductor substrate in a lower-breakdown-voltage MISFET formation region, and a third insulating film for a gate insulating film of a higher-breakdown-voltage MISFET is formed over the semiconductor substrate in a higher-breakdown-voltage MISFET formation region. Subsequently, a film for gate electrodes is formed and then patterned to form the respective gate electrodes of the memory element, the lower-breakdown-voltage MISFET, and the higher-breakdown-voltage MISFET. The step of forming the second insulating film is performed after the step of forming the first insulating film. The step of forming the third insulating film is performed before the step of forming the first insulating film.

    Semiconductor device
    12.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US11342430B2

    公开(公告)日：2022-05-24

    申请号：US17084097

    申请日：2020-10-29

    Applicant: RENESAS ELECTRONICS CORPORATION

    Inventor： Digh Hisamoto ,  Yoshiyuki Kawashima ,  Takashi Hashimoto

    IPC: H01L29/423 ,  H01L21/28 ,  H01L29/10 ,  H01L29/78 ,  H01L29/792 ,  H01L27/11568

    Abstract: A semiconductor device has a split-gate type MONOS structure using a FinFET, and it includes a source and a drain each formed of an n-type impurity diffusion layer, a first channel forming layer which is formed under a control gate and is formed of a semiconductor layer doped with a p-type impurity, and a second channel forming layer which is formed under a memory gate and is formed of a semiconductor layer doped with an n-type impurity. Further, the semiconductor device includes a p-type semiconductor layer which is formed under the second channel forming layer and has an impurity concentration higher than an impurity concentration of a semiconductor substrate.

    Method for manufacturing a semiconductor device
    13.
    发明授权
    Method for manufacturing a semiconductor device 有权

    公开(公告)号：US10777569B2

    公开(公告)日：2020-09-15

    申请号：US16404095

    申请日：2019-05-06

    Applicant: RENESAS ELECTRONICS CORPORATION

    Inventor： Yuto Omizu ,  Takashi Hashimoto ,  Hideaki Yamakoshi

    IPC: H01L21/3065 ,  H01L27/11568 ,  H01L27/1157 ,  H01L27/11565 ,  H01L21/762 ,  H01L21/28

    Abstract: The manufacturing method of the semiconductor device includes a step of forming the gate dielectric film GI2 and the polysilicon layer PS2 on the main surface SUBa of the semiconductor substrate SUB, a step of forming the isolation trench TR in the semiconductor substrate SUB through the polysilicon layer PS2 and the gate dielectric film GI2, a step of filling the isolation trench TR with the dielectric film, and then a step of polishing the dielectric film to form the element isolation film STI in the isolation trench TR. Further, a method for manufacturing a semiconductor device comprises etching the element isolation film STI to retract the upper surface STIa of the element isolation film STI, then further depositing a polysilicon layer on the polysilicon layer PS2 to form a gate electrode using an anisotropic dry etching method.

    Method of manufacturing semiconductor device
    14.
    发明授权
    Method of manufacturing semiconductor device 有权

    公开(公告)号：US10026744B2

    公开(公告)日：2018-07-17

    申请号：US15672909

    申请日：2017-08-09

    Applicant: RENESAS ELECTRONICS CORPORATION

    Inventor： Hideaki Yamakoshi ,  Takashi Hashimoto ,  Shinichiro Abe ,  Yuto Omizu

    IPC: H01L27/112 ,  H01L27/11563

    Abstract: An improvement is achieved in the reliability of a semiconductor device. A structure is obtained in which a first insulating film for a gate insulating film of a memory element is formed over a semiconductor substrate located in a memory region, a second insulating film for a gate insulating film of a lower-breakdown-voltage MISFET is formed over the semiconductor substrate located in a lower-breakdown-voltage MISFET formation region, and a third insulating film for a gate insulating film of a higher-breakdown-voltage MISFET is formed over the semiconductor substrate located in a higher-breakdown-voltage MISFET formation region. Subsequently, a film for gate electrodes is formed and then patterned to form the respective gate electrodes of the memory element, the lower-breakdown-voltage MISFET, and the higher-breakdown-voltage MISFET. The step of forming the second insulating film is performed after the step of forming the first insulating film. The step of forming the third insulating film is performed before the step of forming the first insulating film.

    Method of manufacturing semiconductor device
    16.
    发明授权
    Method of manufacturing semiconductor device 有权
    制造半导体器件的方法

    公开(公告)号：US09263291B2

    公开(公告)日：2016-02-16

    申请号：US14079120

    申请日：2013-11-13

    Applicant: Renesas Electronics Corporation

    Inventor： Koichi Toba ,  Hiraku Chakihara ,  Yoshiyuki Kawashima ,  Kentaro Saito ,  Takashi Hashimoto

    IPC: H01L21/44 ,  H01L21/3105 ,  H01L27/092 ,  H01L29/423 ,  H01L29/66 ,  H01L27/115 ,  H01L21/8234

    CPC classification number: H01L29/7847 ,  H01L21/28282 ,  H01L21/28518 ,  H01L21/3105 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823468 ,  H01L27/0922 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/66825 ,  H01L29/66833

    Abstract: To improve a semiconductor device having a nonvolatile memory. a first MISFET, a second MISFET, and a memory cell are formed, and a stopper film made of a silicon oxide film is formed thereover. Then, over the stopper film, a stress application film made of a silicon nitride film is formed, and the stress application film over the second MISFET and the memory cell is removed. Thereafter, heat treatment is performed to apply a stress to the first MISFET. Thus, a SMT is not applied to each of elements, but is applied selectively. This can reduce the degree of degradation of the second MISFET due to H (hydrogen) in the silicon nitride film forming the stress application film. This can also reduce the degree of degradation of the characteristics of the memory cell due to the H (hydrogen) in the silicon nitride film forming the stress application film.

    Abstract translation: 改善具有非易失性存储器的半导体器件。 形成第一MISFET，第二MISFET和存储单元，并在其上形成由氧化硅膜制成的阻挡膜。 然后，在阻挡膜上形成由氮化硅膜构成的应力施加膜，除去第二MISFET和存储单元上的应力施加膜。 此后，进行热处理以向第一MISFET施加应力。 因此，SMT不应用于每个元件，而是被选择性地应用。 这可以降低由于形成应力施加膜的氮化硅膜中的H（氢）导致的第二MISFET的劣化程度。 这也可以由于形成应力施加膜的氮化硅膜中的H（氢）而降低存储单元的特性的劣化程度。

    Semiconductor device and a method of manufacturing the same
    17.
    发明授权
    Semiconductor device and a method of manufacturing the same 有权
    半导体装置及其制造方法

    公开(公告)号：US08975678B2

    公开(公告)日：2015-03-10

    申请号：US13867213

    申请日：2013-04-22

    Applicant: Renesas Electronics Corporation

    Inventor： Yoshiyuki Kawashima ,  Koichi Toba ,  Yasushi Ishii ,  Toshikazu Matsui ,  Takashi Hashimoto

    IPC: H01L49/02 ,  H01L27/06 ,  H01L27/08 ,  H01L27/105 ,  H01L27/115

    CPC classification number: H01L28/60 ,  H01L27/0629 ,  H01L27/0805 ,  H01L27/105 ,  H01L27/10805 ,  H01L27/11526 ,  H01L27/11531 ,  H01L27/11573 ,  H01L28/40

    Abstract: In connection with a semiconductor device including a capacitor element there is provided a technique capable of improving the reliability of the capacitor element. A capacitor element is formed in an element isolation region formed over a semiconductor substrate. The capacitor element includes a lower electrode and an upper electrode formed over the lower electrode through a capacitor insulating film. Basically, the lower electrode and the upper electrode are formed from polysilicon films and a cobalt silicide film formed over the surfaces of the polysilicon films. End portions of the cobalt silicide film formed over the upper electrode are spaced apart a distance from end portions of the upper electrode. Besides, end portions of the cobalt silicide film formed over the lower electrode are spaced apart a distance from boundaries between the upper electrode and the lower electrode.

    Abstract translation: 关于包括电容器元件的半导体器件，提供了一种能够提高电容器元件的可靠性的技术。 电容器元件形成在半导体衬底上形成的元件隔离区域中。 电容器元件包括通过电容器绝缘膜形成在下电极上的下电极和上电极。 基本上，下电极和上电极由形成在多晶硅膜的表面上的多晶硅膜和硅化钴膜形成。 形成在上电极上的钴硅化物膜的端部与上电极的端部间隔开一定距离。 此外，形成在下电极上的钴硅化物膜的端部与上电极和下电极之间的边界间隔一定距离。

Patent Agency Ranking