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42 条记录 (耗时 0.029 秒)

    Fully depleted silicon on insulator semiconductor devices
    11.
    发明授权
    Fully depleted silicon on insulator semiconductor devices 有权
    完全耗尽的绝缘体上硅绝缘体器件

    公开(公告)号：US07385436B2

    公开(公告)日：2008-06-10

    申请号：US11714844

    申请日：2007-03-07

    申请人： Kiyoo Itoh ,  Ryuta Tsuchiya ,  Takayuki Kawahara

    发明人： Kiyoo Itoh ,  Ryuta Tsuchiya ,  Takayuki Kawahara

    IPC分类号： H03K3/01

    CPC分类号： H01L21/84 ,  H01L27/1203 ,  H01L29/66772 ,  H01L29/78648 ,  H03K19/0027 ,  H03K19/00384 ,  H03K19/018585

    摘要： A CMOS circuit in low-voltage implementation, low power-consumption implementation, high-speed implementation, or small-size implementation. In a circuit which uses a FD-SOI MOST where a back gate is controlled by a well, voltage amplitude at the well is made larger than input-voltage amplitude at the gate. Alternatively, the circuit is modified into a circuit which uses a MOST that changes dynamically into an enhancement mode and a depletion mode.

    摘要翻译： CMOS电路在低电压实现，低功耗实现，高速实现或小尺寸实现。 在使用背阱由阱控制的FD-SOI MOST的电路中，阱处的电压振幅大于栅极处的输入电压幅度。 或者，电路被修改为使用将动态变化为增强模式和耗尽模式的MOST的电路。

    Solar Cell
    14.
    发明申请
    Solar Cell 审中-公开
    太阳能电池

    公开(公告)号：US20120318337A1

    公开(公告)日：2012-12-20

    申请号：US13521487

    申请日：2012-02-17

    申请人： Keiji Watanabe ,  Takashi Hattori ,  Mieko Matsumura ,  Ryuta Tsuchiya ,  Mutsuko Hatano

    发明人： Keiji Watanabe ,  Takashi Hattori ,  Mieko Matsumura ,  Ryuta Tsuchiya ,  Mutsuko Hatano

    IPC分类号： H01L31/076

    CPC分类号： H01L31/075 ,  H01L31/022441 ,  H01L31/0504 ,  H01L31/0508 ,  H01L31/0512 ,  H01L31/1804 ,  Y02E10/547 ,  Y02E10/548 ,  Y02P70/521

    摘要： In a conventional solar cell, it has been difficult to ensure a sufficient light absorption and simultaneously to prevent current loss due to the reduction of the moving distance of electrons and holes. As a means for solving this difficulty, a plurality of a p-i-n junctions are stacked through an insulating film and are connected in parallel with each other using through-electrodes. In this case, the through-electrodes and the p-i-n junctions are connected through the p-layer or the n-layer, thereby moving electrons and holes in opposite directions and generating output current. In addition, the i-layer is made thicker than the p-layer and the n-layer in each of the p-i-n junctions, thereby ensuring a sufficient light absorption and simultaneously preventing current loss.

    摘要翻译： 在常规太阳能电池中，难以确保足够的光吸收并且同时防止由于电子和空穴的移动距离的减小导致的电流损耗。 作为解决这个困难的手段，通过绝缘膜层叠多个p-i-n结，并且使用贯通电极彼此并联连接。 在这种情况下，贯通电极和p-i-n结通过p层或n层连接，从而沿相反方向移动电子和空穴并产生输出电流。 此外，i层比p-i-n结中的每一个中的p层和n层厚，从而确保足够的光吸收并同时防止电流损耗。

    Semiconductor device
    15.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US08183635B2

    公开(公告)日：2012-05-22

    申请号：US12756451

    申请日：2010-04-08

    申请人： Nobuyuki Sugii ,  Ryuta Tsuchiya ,  Shinichiro Kimura ,  Takashi Ishigaki ,  Yusuke Morita ,  Hiroyuki Yoshimoto

    发明人： Nobuyuki Sugii ,  Ryuta Tsuchiya ,  Shinichiro Kimura ,  Takashi Ishigaki ,  Yusuke Morita ,  Hiroyuki Yoshimoto

    IPC分类号： H01L21/00

    CPC分类号： H01L27/1203 ,  H01L21/76283

    摘要： A technique to be applied to a semiconductor device for achieving low power consumption by improving a shape at a boundary portion of a shallow trench and an SOI layer of an SOI substrate. A position (SOI edge) at which a main surface of a silicon substrate and a line extended along a side surface of an SOI layer are crossed is recessed away from a shallow-trench isolation more than a position (STI edge) at which a line extended along a sidewall of a shallow trench and a line extended along the main surface of the silicon substrate are crossed, and a corner of the silicon substrate at the STI edge has a curved surface.

    摘要翻译： 通过改善在SOI衬底的浅沟槽和SOI层的边界部分的形状来实现低功耗的半导体器件的技术。 硅衬底的主表面和沿着SOI层的侧表面延伸的线交叉的位置（SOI边缘）比浅沟槽隔离更远离位于（STI边缘）的位置（STI边缘），在该位置处 沿着浅沟槽的侧壁延伸并且沿着硅衬底的主表面延伸的线交叉，并且在STI边缘处的硅衬底的拐角具有弯曲表面。

    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
    16.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 失效
    半导体器件及其制造方法

    公开(公告)号：US20100258871A1

    公开(公告)日：2010-10-14

    申请号：US12759559

    申请日：2010-04-13

    申请人： Takashi Ishigaki ,  Ryuta Tsuchiya ,  Yusuke Morita ,  Nobuyuki Sugii

    发明人： Takashi Ishigaki ,  Ryuta Tsuchiya ,  Yusuke Morita ,  Nobuyuki Sugii

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L29/785 ,  H01L29/66795

    摘要： Characteristics of a semiconductor device having a FINFET are improved. The FINFET has: a channel layer arranged in an arch shape on a semiconductor substrate and formed of monocrystalline silicon; a front gate electrode formed on a part of an outside of the channel layer through a front gate insulating film; and a back gate electrode formed so as to be buried inside the channel layer through a back gate insulating film. The back gate electrode arranged inside the arch shape is arranged so as to pass through the front gate electrode.

    摘要翻译： 具有FINFET的半导体器件的特性得到改善。 FINFET具有：在半导体衬底上以拱形形式布置并由单晶硅形成的沟道层; 前栅电极，其通过前栅极绝缘膜形成在沟道层的外部的一部分上; 以及形成为通过背栅绝缘膜埋设在沟道层内的背栅电极。 布置在拱形内侧的背栅极布置成穿过前栅电极。

    Semiconductor devices
    19.
    发明申请
    Semiconductor devices 失效
    半导体器件

    公开(公告)号：US20070008027A1

    公开(公告)日：2007-01-11

    申请号：US11362172

    申请日：2006-02-27

    申请人： Kiyoo Itoh ,  Ryuta Tsuchiya ,  Takayuki Kawahara

    发明人： Kiyoo Itoh ,  Ryuta Tsuchiya ,  Takayuki Kawahara

    IPC分类号： H03K3/01

    CPC分类号： H01L21/84 ,  H01L27/1203 ,  H01L29/66772 ,  H01L29/78648 ,  H03K19/0027 ,  H03K19/00384 ,  H03K19/018585

    摘要： A CMOS circuit in low-voltage implementation, low power-consumption implementation, high-speed implementation, or small-size implementation. In a circuit which uses a FD-SOI MOST where a back gate is controlled by a well, voltage amplitude at the well is made larger than input-voltage amplitude at the gate. Alternatively, the circuit is modified into a circuit which uses a MOST that changes dynamically into an enhancement mode and a depletion mode.

    摘要翻译： CMOS电路在低电压实现，低功耗实现，高速实现或小尺寸实现。 在使用背阱由阱控制的FD-SOI MOST的电路中，阱处的电压振幅大于栅极处的输入电压幅度。 或者，电路被修改为使用将动态变化为增强模式和耗尽模式的MOST的电路。

    Semiconductor device
    20.
    发明申请
    Semiconductor device 审中-公开
    半导体器件

    公开(公告)号：US20060001111A1

    公开(公告)日：2006-01-05

    申请号：US11155674

    申请日：2005-06-20

    申请人： Ryuta Tsuchiya ,  Shinichi Sato ,  Masatada Horiuchi

    发明人： Ryuta Tsuchiya ,  Shinichi Sato ,  Masatada Horiuchi

    IPC分类号： H01L29/76 ,  H01L21/8238

    CPC分类号： H01L29/78696 ,  H01L21/28185 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/458 ,  H01L29/4908 ,  H01L29/4925 ,  H01L29/4933 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66772

    摘要： In a full depletion MISFET, there is a limit to control on a threshold voltage Vth by an impurity concentration in principle when a monocrystalline SOI layer becomes thin on the order of a few tens of nm. It was thus difficult to simultaneously realize predetermined Vth of both n and p types in a complementary MISFET. A gate insulating film for the MISFET is formed as a laminated layer of a metal oxide and an oxynitride. A gate electrode is formed using a polycrystalline Si semiconductor film of the same conductivity type as a source-drain. Predetermined Vth for enhancement are simultaneously achieved by a shift of a flatband voltage produced between the gate insulating film and the gate electrode made of the semiconductor film. Since a variation in Vth due to a statistical fluctuation in the number of impurities with respect to one MISFET can be reduced as compared with the case in which each Vth is controlled by the impurity concentration, Vth and a power supply voltage can both be set low.

    摘要翻译： 在完全耗尽的MISFET中，当单晶SOI层变薄到数十nm左右时，在原理上控制阈值电压Vth的限制是有限的。 因此难以在互补的MISFET中同时实现n和p类型的预定Vth。 形成用于MISFET的栅极绝缘膜作为金属氧化物和氧氮化物的叠层。 使用与源极 - 漏极相同的导电类型的多晶硅半导体膜形成栅电极。 用于增强的预定Vth同时通过栅极绝缘膜和由半导体膜制成的栅电极之间产生的平带电压的偏移来实现。 由于相对于一个MISFET而言由于杂质数统计上的波动导致的Vth的变化，与各种Vth被杂质浓度控制的情况相比，可以降低Vth和电源电压两者 。