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    Semiconductor memory device
    2.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US07609572B2

    公开(公告)日：2009-10-27

    申请号：US11963831

    申请日：2007-12-22

    申请人： Hiroaki Nakaya ,  Riichiro Takemura ,  Satoru Akiyama ,  Tomonori Sekiguchi ,  Masayuki Nakamura ,  Shinichi Miyatake

    发明人： Hiroaki Nakaya ,  Riichiro Takemura ,  Satoru Akiyama ,  Tomonori Sekiguchi ,  Masayuki Nakamura ,  Shinichi Miyatake

    IPC分类号： G11C7/00

    CPC分类号： G11C11/4091 ,  G11C7/08 ,  G11C2207/005

    摘要： In a semiconductor memory device, with respect to low voltage application, technique of controlling a gate voltage of a shared MOS transistor increasing sense speed and increasing data read speed by preventing data inversion caused by noise and reducing bit line capacitance during sensing is provided. By a shared MOS transistor gate voltage control circuit connecting a sense amplifier and a memory cell array, a shared MOS transistor gate voltage (SHR) is lowered in two stages and bit line capacitance to be amplified is reduced taking noise during the sensing into consideration so that the sense speed is increased. Therefore, a timing of activating a column selection signal can be hastened and as a result, data read time can be reduced.

    摘要翻译： 在半导体存储器件中，关于低电压应用，提供了通过防止由噪声引起的数据反转和降低感测期间的位线电容来控制共享MOS晶体管的栅极电压提高感测速度并增加数据读取速度的技术。 通过连接读出放大器和存储单元阵列的共享MOS晶体管栅极电压控制电路，共享的MOS晶体管栅极电压（SHR）分为两级降低，并且在感测期间考虑到噪声，放大的位线电容降低 感觉速度增加。 因此，可以加快激活列选择信号的定时，结果可以减少数据读取时间。

    Semiconductor memory device
    3.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US07633833B2

    公开(公告)日：2009-12-15

    申请号：US12028788

    申请日：2008-02-09

    申请人： Riichiro Takemura ,  Tomonori Sekiguchi ,  Satoru Akiyama ,  Hiroaki Nakaya ,  Masayuki Nakamura

    发明人： Riichiro Takemura ,  Tomonori Sekiguchi ,  Satoru Akiyama ,  Hiroaki Nakaya ,  Masayuki Nakamura

    IPC分类号： G11C8/00

    CPC分类号： G11C7/04 ,  G11C7/1066 ,  G11C7/1072 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4076 ,  G11C2207/2272

    摘要： The semiconductor memory device according to the invention is provided with a first delay circuit block that generates a timing signal of a circuit block to be operated in column cycle time determined by an external input command cycle and a second delay circuit block the whole delay of which is controlled to be a difference between access time determined by an external clock and the latency and column cycle time. These delay circuit blocks are controlled so that the delay of each delay circuit is a suitable value in accordance with column latency and an operating frequency, and each delay is controlled corresponding to dispersion in a process and operating voltage and a change of operating temperature.

    摘要翻译： 根据本发明的半导体存储器件具有第一延迟电路块，该第一延迟电路块产生在由外部输入指令周期确定的列周期时间内操作的电路块的定时信号，而第二延迟电路阻止其整个延迟 被控制为由外部时钟确定的访问时间与延迟和列周期时间之间的差异。 控制这些延迟电路块，使得每个延迟电路的延迟是根据列等待时间和工作频率的合适值，并且根据工艺中的色散和工作电压以及工作温度的变化控制每个延迟。

    SEMICONDUCTOR MEMORY DEVICE
    4.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 失效
    半导体存储器件

    公开(公告)号：US20080239865A1

    公开(公告)日：2008-10-02

    申请号：US12028788

    申请日：2008-02-09

    申请人： Riichiro TAKEMURA ,  Tomonori Sekiguchi ,  Satoru Akiyama ,  Hiroaki Nakaya ,  Masayuki Nakamura

    发明人： Riichiro TAKEMURA ,  Tomonori Sekiguchi ,  Satoru Akiyama ,  Hiroaki Nakaya ,  Masayuki Nakamura

    IPC分类号： G11C8/00

    CPC分类号： G11C7/04 ,  G11C7/1066 ,  G11C7/1072 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4076 ,  G11C2207/2272

    摘要： The semiconductor memory device according to the invention is provided with a first delay circuit block that generates a timing signal of a circuit block to be operated in column cycle time determined by an external input command cycle and a second delay circuit block the whole delay of which is controlled to be a difference between access time determined by an external clock and the latency and column cycle time. These delay circuit blocks are controlled so that the delay of each delay circuit is a suitable value in accordance with column latency and an operating frequency, and each delay is controlled corresponding to dispersion in a process and operating voltage and a change of operating temperature.

    摘要翻译： 根据本发明的半导体存储器件具有第一延迟电路块，该第一延迟电路块产生在由外部输入指令周期确定的列周期时间内操作的电路块的定时信号，而第二延迟电路阻止其整个延迟 被控制为由外部时钟确定的访问时间与延迟和列周期时间之间的差异。 控制这些延迟电路块，使得每个延迟电路的延迟是根据列等待时间和工作频率的合适值，并且根据工艺中的色散和工作电压以及工作温度的变化控制每个延迟。

    SEMICONDUCTOR MEMORY DEVICE
    5.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 失效
    半导体存储器件

    公开(公告)号：US20080181026A1

    公开(公告)日：2008-07-31

    申请号：US11963831

    申请日：2007-12-22

    申请人： Hiroaki Nakaya ,  Riichiro Takemura ,  Satoru Akiyama ,  Tomonori Sekiguchi ,  Masayuki Nakamura ,  Shinichi Miyatake

    发明人： Hiroaki Nakaya ,  Riichiro Takemura ,  Satoru Akiyama ,  Tomonori Sekiguchi ,  Masayuki Nakamura ,  Shinichi Miyatake

    IPC分类号： G11C7/08

    CPC分类号： G11C11/4091 ,  G11C7/08 ,  G11C2207/005

    摘要： In a semiconductor memory device, with respect to low voltage application, technique of controlling a gate voltage of a shared MOS transistor increasing sense speed and increasing data read speed by preventing data inversion caused by noise and reducing bit line capacitance during sensing is provided. By a shared MOS transistor gate voltage control circuit connecting a sense amplifier and a memory cell array, a shared MOS transistor gate voltage (SHR) is lowered in two stages and bit line capacitance to be amplified is reduced taking noise during the sensing into consideration so that the sense speed is increased. Therefore, a timing of activating a column selection signal can be hastened and as a result, data read time can be reduced.

    摘要翻译： 在半导体存储器件中，关于低电压应用，提供了通过防止由噪声引起的数据反转和降低感测期间的位线电容来控制共享MOS晶体管的栅极电压提高感测速度并增加数据读取速度的技术。 通过连接读出放大器和存储单元阵列的共享MOS晶体管栅极电压控制电路，共享的MOS晶体管栅极电压（SHR）分为两级降低，并且在感测期间考虑到噪声，放大的位线电容降低 感觉速度增加。 因此，可以加快激活列选择信号的定时，结果可以减少数据读取时间。

    Large-capacity semiconductor memory with improved layout for sub-amplifiers to increase speed
    10.
    再颁专利
    Large-capacity semiconductor memory with improved layout for sub-amplifiers to increase speed 有权
    大容量半导体存储器，具有改进的子放大器布局，以提高速度

    公开(公告)号：USRE42659E1

    公开(公告)日：2011-08-30

    申请号：US11759316

    申请日：2007-06-07

    申请人： Tsugio Takahashi ,  Goro Kitsukawa ,  Takesada Akiba ,  Yasushi Kawase ,  Masayuki Nakamura

    发明人： Tsugio Takahashi ,  Goro Kitsukawa ,  Takesada Akiba ,  Yasushi Kawase ,  Masayuki Nakamura

    IPC分类号： G11C8/00

    CPC分类号： H01L27/10805 ,  G11C7/10 ,  G11C11/408 ,  G11C11/4096 ,  G11C11/4097 ,  H01L27/105

    摘要： A semiconductor memory such as a dynamic RAM having memory mats each divided into a plurality of units or sub-memory mats. Each sub-memory mat comprises: a memory array having sub-word lines and sub-bit lines intersecting orthogonally and dynamic memory cells located in lattice fashion at the intersection points between the intersecting sub-word and sub-bit lines; a sub-word line driver including unit sub-word line driving circuits corresponding to the sub-word lines; a sense amplifier including unit amplifier circuits and column selection switches corresponding to the sub-bit lines; and sub-common I/O lines to which designated sub-bit lines are connected selectively via the column selection switches. The sub-memory mats are arranged in lattice fashion. Above the sub-memory mats is a layer of: main word lines and column selection signal lines intersecting orthogonally, the main word lines having a pitch that is an integer multiple of the pitch of the sub-word lines, the column selection signal lines having a pitch that is an integer multiple of the pitch of the sub-bit lines; and main common I/O lines to which designated sub-common I/O lines are connected selectively.

    摘要翻译： 具有各自被划分为多个单元或子存储器垫的存储器垫的动态RAM等半导体存储器。 每个子存储器垫包括：存储器阵列，其具有在相交的子字和子位线之间的交叉点处以网格方式位于正交和动态存储器单元的子字线和子位线; 子字线驱动器，包括对应于子字线的单元子字线驱动电路; 感测放大器，包括对应于子位线的单位放大器电路和列选择开关; 以及经由列选择开关选择性地连接指定子位线的子公共I / O线。 子存储垫以格子排列。 在子存储器衬垫之上是与主要字线和列选择信号线正交相交的层，主字线具有作为子字线的间距的整数倍的间距，列选择信号线具有 间距，是子位线的间距的整数倍; 以及指定的子公共I / O线选择性地连接的主要公共I / O。