公开(公告)号：US20220102390A1

公开(公告)日：2022-03-31

申请号：US17342088

申请日：2021-06-08

Applicant: Samsung Display Co., LTD.

Inventor： Keum Hee LEE ,  Dong Hoon SHIN ,  June Whan CHOI ,  Seung Sok SON ,  Woo Geun LEE

IPC: H01L27/12

Abstract: A display device includes a base layer; a first pattern disposed on the base layer; an insulating layer disposed on the first pattern and including layers; and a second pattern disposed on the insulating layer. At least two of the layers of the insulating layer include a same material.

公开(公告)号：US20160027805A1

公开(公告)日：2016-01-28

申请号：US14875320

申请日：2015-10-05

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Hye Young RYU ,  Hee Jun BYEON ,  Woo Geun LEE ,  Kap Soo YOON ,  Yoon Ho KIM ,  Chun Won BYUN

IPC: H01L27/12 ,  G02F1/1368 ,  G02F1/1362

CPC classification number: H01L27/127 ,  G02F1/134363 ,  G02F1/136227 ,  G02F1/136286 ,  G02F1/1368 ,  G02F2001/136222 ,  G02F2001/136295 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1248 ,  H01L27/1262

Abstract: A thin film transistor array panel and a manufacturing method thereof according to an exemplary embodiment of the present invention form a contact hole in a second passivation layer formed of an organic insulator, protect a side of the contact hole by covering with a protection member formed of the same layer as the first field generating electrode and formed of a transparent conductive material, and etch the first passivation layer below the second passivation layer using the protection member as a mask. Therefore, it is possible to prevent the second passivation layer formed of an organic insulator from being overetched while etching the insulating layer below the second passivation layer so that the contact hole is prevented from being made excessively wide.

公开(公告)号：US20150187813A1

公开(公告)日：2015-07-02

申请号：US14659120

申请日：2015-03-16

Applicant: Samsung Display Co., Ltd.

Inventor： Seung-Ho JUNG ,  Young Joo CHOI ,  Joon Geol KIM ,  Kang Moon JO ,  Sho Yeon KIM ,  Byung Hwan CHU ,  Woo Geun LEE ,  Woo-Seok JEON

IPC: H01L27/12

CPC classification number: H01L27/124 ,  H01L27/1214 ,  H01L27/1225 ,  H01L27/1248 ,  H01L27/1259 ,  H01L27/1262 ,  H01L27/1288

Abstract: A thin film transistor array panel is disclosed. The thin film transistor array panel may include a gate line disposed on a substrate and including a gate electrode, a semiconductor layer including an oxide semiconductor disposed on the substrate, a data wiring layer disposed on the substrate and including a data line crossing the gate line, a source electrode connected to the data line and a drain electrode facing the source electrode, a polymer layer covering the source electrode and the drain electrode, and a passivation layer disposed on the polymer layer. The data wiring layer may include copper or a copper alloy and the polymer layer may include fluorocarbon.

Abstract translation: 公开了薄膜晶体管阵列面板。 薄膜晶体管阵列面板可以包括设置在基板上并包括栅电极的栅极线，包括设置在基板上的氧化物半导体的半导体层，设置在基板上的数据布线层，并且包括与栅极线交叉的数据线 连接到数据线的源电极和面对源电极的漏电极，覆盖源电极和漏电极的聚合物层和设置在聚合物层上的钝化层。 数据布线层可以包括铜或铜合金，并且聚合物层可以包括碳氟化合物。

公开(公告)号：US20240431161A1

公开(公告)日：2024-12-26

申请号：US18398191

申请日：2023-12-28

Applicant: Samsung Display Co., Ltd.

Inventor： Jong In KIM ,  Hyun Seong KANG ,  Yoo Mi RA ,  Seung Sok SON ,  Kap Soo YOON ,  Keum Hee LEE ,  Doo Young LEE ,  Seong Young LEE ,  Woo Geun LEE ,  Ji Yun HONG

IPC: H10K59/131 ,  G09G3/3233 ,  H10K59/121

Abstract: A display device is provided. The display device comprises a first voltage line, a data line, a first capacitor electrode, a buffer layer disposed on the first voltage line, a second capacitor electrode disposed on the first capacitor electrode to overlap the first capacitor electrode in a plan view, a first transistor disposed on the buffer layer and connected to the data line, an interlayer insulating layer disposed on the second capacitor electrode, and a first connection pattern disposed on the interlayer insulating layer and connected to the second capacitor electrode and the first transistor, wherein the first connection pattern is connected to the second capacitor electrode through a contact hole formed through the interlayer insulating layer and connected to the first transistor through a contact hole formed through the interlayer insulating layer, and the first capacitor electrode overlaps the first connection pattern.

公开(公告)号：US20240414956A1

公开(公告)日：2024-12-12

申请号：US18398197

申请日：2023-12-28

Applicant: Samsung Display Co., Ltd.

Inventor： Jae Hyun LEE ,  Seung Ha CHOI ,  Ye Eun KANG ,  Jong Bum CHOI ,  Seung Rae KIM ,  Woo Geun LEE

IPC: H10K59/123 ,  G09G3/32

Abstract: A display device includes a first pixel and a second pixel. The first pixel and the second pixel each includes a first transistor, a portion of a via layer disposed on the first transistor, and a portion of a first metal layer disposed on the via layer. The first pixel and the second pixel further include a first pixel electrode and a second pixel electrode disposed in the first metal layer, and a first end of the first pixel electrode faces the second pixel electrode and is positioned at a height lower than the second pixel electrode.

公开(公告)号：US20240324320A1

公开(公告)日：2024-09-26

申请号：US18517068

申请日：2023-11-22

Applicant: Samsung Display Co., LTD.

Inventor： Ki Won KIM ,  Jeong Ju PARK ,  Seung Sok SON ,  Kap Soo YOON ,  Woo Geun LEE ,  Ji Yun HONG

IPC: H10K59/123 ,  H10K59/12 ,  H10K71/60

CPC classification number: H10K59/123 ,  H10K59/1201 ,  H10K71/60

Abstract: A method for fabricating a display device includes providing a substrate into a chamber; forming an active material layer on the substrate by a plurality of deposition processes in the chamber; forming an active layer by patterning the active material layer: forming a transistor including a gate electrode overlapping the active layer; and forming a pixel electrode on the transistor, at least two deposition processes among the plurality of deposition processes are performed by applying different magnitudes of power, respectively.

公开(公告)号：US20240122006A1

公开(公告)日：2024-04-11

申请号：US18238550

申请日：2023-08-28

Applicant: Samsung Display Co., LTD.

Inventor： Shin Hyuk YANG ,  Dong Han KANG ,  Jee Hoon KIM ,  Sung Gwon MOON ,  Seung Sok SON ,  Woo Geun LEE

IPC: H10K59/131 ,  H10K59/12 ,  H10K59/122

CPC classification number: H10K59/131 ,  H10K59/1201 ,  H10K59/122

Abstract: A display device includes a data conductive layer including a first power line, a passivation layer with a first opening exposing the first power line, a via layer with a second opening partially overlapping the first opening, a pixel electrode on the via layer, a connection electrode in the first and second openings, a pixel-defining film with an opening overlapping the second opening, a light-emitting layer on the pixel-defining film, the pixel electrode and the connection electrode, and a common electrode connected to the first power line. The data conductive layer includes a data base layer, a data main metal layer, and a data capping layer, the first power line includes a wire connection structure, in which the data main metal layer is recessed from sides of the data capping layer, and the common electrode is connected to the data main metal layer in the wire connection structure.

公开(公告)号：US20220157915A1

公开(公告)日：2022-05-19

申请号：US17465795

申请日：2021-09-02

Applicant: Samsung Display Co., Ltd.

Inventor： Woo Geun LEE ,  Young Jae Jeon ,  Woo Bin Lee ,  Jin Won Lee

IPC: H01L27/32

Abstract: A display device including a substrate; a signal line disposed on the substrate and to which a predetermined voltage signal is applied; a power auxiliary line to which a first source voltage is applied; a first driving voltage line to which a first driving voltage higher than the first source voltage is applied; and a first transistor disposed between the signal line and the first driving voltage line. The first transistor includes a first lower gate electrode connected to the power auxiliary line and a first upper gate electrode connected to the signal line.

公开(公告)号：US20220005402A1

公开(公告)日：2022-01-06

申请号：US17478825

申请日：2021-09-17

Applicant: Samsung Display Co., Ltd.

Inventor： Kang Nam KIM ,  Sung Hoon LIM ,  Woo Geun LEE ,  Kyu Sik CHO ,  Jae Beom CHOI

IPC: G09G3/20

Abstract: A scan driver includes a plurality of stages. An nth (n is a natural number) stage among the stages includes: a first and a second input circuit for controlling a voltage of a first node in response to a carry signal of a previous stage and a next stage, respectively; a first output circuit for outputting an nth carry signal corresponding to a carry clock signal in response to the voltage of the first node; a second output circuit for outputting an nth scan and an nth sensing signal corresponding to a scan and a sensing clock signal, respectively, in response to the voltage of the first node; and a sampling circuit for storing the carry signal of the previous stage in response to a first select signal, and for supplying a control voltage to the first node in response to a second select signal and the stored carry signal.

公开(公告)号：US20210091163A1

公开(公告)日：2021-03-25

申请号：US16892988

申请日：2020-06-04

Applicant: Samsung Display Co., LTD.

Inventor： Seung Sok SON ,  Woo Geun LEE ,  Seul Ki KIM ,  Kap Soo YOON ,  Hyun Woong BAEK ,  Jae Hyun LEE ,  Su Jung JUNG ,  Jung Kyoung CHO ,  Seung Ha CHOI ,  June Whan CHOI

IPC: H01L27/32 ,  G09G3/32

Abstract: A display device includes a substrate, a first conductive layer on the substrate, the first conductive layer including a data signal line, a first insulating layer on the first conductive layer, a semiconductor layer on the first insulating layer, the semiconductor layer including a first semiconductor pattern, a second insulating layer on the semiconductor layer, and a second conductive layer on the second insulating layer, the second conductive layer including a gate electrode disposed to overlap the first semiconductor pattern, a transistor first electrode disposed to overlap a part of the first semiconductor pattern, wherein the transistor first electrode is electrically connected to the data signal line through a contact hole that penetrates the first and second insulating layers, and a transistor second electrode disposed to overlap another part of the first semiconductor pattern.