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公开(公告)号:US20140167239A1
公开(公告)日:2014-06-19
申请号:US14106107
申请日:2013-12-13
Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
Inventor: Tae Hyun Kim , Do Jae Yoo , Bum Seok Suh
IPC: H01L23/495
CPC classification number: H01L23/3735 , H01L23/053 , H01L23/3121 , H01L23/4334 , H01L23/49531 , H01L23/49575 , H01L23/49811 , H01L2224/32225 , H01L2224/48091 , H01L2224/48137 , H01L2224/48227 , H01L2224/48247 , H01L2224/73265 , H01L2924/13034 , H01L2924/1305 , H01L2924/13055 , H01L2924/13091 , H01L2924/181 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
Abstract: Disclosed herein is a power module package including: a substrate including a metal layer, a first insulation layer formed on the metal layer, a first circuit pattern formed on the first insulation layer and including a first pad and a second pad spaced apart from the first pad, a second insulation layer formed on the first insulation layer to cover the first circuit pattern, and a second circuit pattern formed on the second insulation layer and including a third pad formed on a location corresponding to the first pad and a fourth pad spaced apart from the third pad; a semiconductor chip mounted on the second circuit pattern; one end being electrically connected to the semiconductor chip, and another end protruding from the outside, wherein the first pad and the third pad, and the second pad and the fourth pad have different polarities.
Abstract translation: 本文公开了一种功率模块封装,包括:基板,包括金属层,形成在金属层上的第一绝缘层,形成在第一绝缘层上的第一电路图案,并且包括第一焊盘和与第一绝缘层间隔开的第二焊盘 衬垫,形成在所述第一绝缘层上以覆盖所述第一电路图案的第二绝缘层,以及形成在所述第二绝缘层上并包括形成在与所述第一焊盘相对应的位置的第三焊盘和间隔开的第四焊盘的第二焊盘图案 从第三垫; 安装在第二电路图案上的半导体芯片; 一端电连接到半导体芯片,另一端从外部突出,其中第一焊盘和第三焊盘以及第二焊盘和第四焊盘具有不同的极性。
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公开(公告)号:US20240032201A1
公开(公告)日:2024-01-25
申请号:US18102285
申请日:2023-01-27
Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
Inventor: Do Jae Yoo , Yong Gil Namgung , Jong Hoon Shin , Won Ju Jang , Yun Hwan Kim
CPC classification number: H05K1/185 , H05K1/0306 , H05K1/053 , H05K1/0296 , H05K3/10 , H05K2203/013 , H05K2201/0206
Abstract: A printed circuit board (PCB) includes a solder resist layer including at least one of an opening and a depression and a solder resist patch disposed in at least one of the opening and the depression to have an interface with the solder resist layer in at least one of the opening and the depression.
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公开(公告)号:US11387270B2
公开(公告)日:2022-07-12
申请号:US16535123
申请日:2019-08-08
Applicant: Samsung Electro-Mechanics Co., Ltd.
Inventor: Do Jae Yoo , Byoung Heon Kim , Yong Gil Namgung , Jong Cheol Hong , Si Joong Yang
IPC: H01L27/146 , H01L23/00
Abstract: An image sensor package includes a substrate, an image sensor mounted on the substrate, a bonding wire connecting the image sensor to the substrate, a reflector disposed on the image sensor, a sealing member sealing the bonding wire and a portion of the image sensor, and covering at least a portion of the reflector, the sealing member including a hole exposing an effective imaging plane of the image sensor, and a filter attached to the sealing member.
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14.
公开(公告)号:US09343391B2
公开(公告)日:2016-05-17
申请号:US14296061
申请日:2014-06-04
Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
Inventor: Kyu Hwan Oh , Do Jae Yoo
IPC: H01L31/062 , H01L23/48 , H01L21/56 , H01L21/768 , H01L23/31
CPC classification number: H01L23/481 , H01L21/565 , H01L21/76816 , H01L23/3121 , H01L23/49827 , H01L24/19 , H01L25/03 , H01L25/16 , H01L2224/04105 , H01L2224/18 , H01L2924/0002 , H01L2924/19105 , H01L2924/19106 , H01L2924/00
Abstract: Disclosed herein are a semiconductor package and a method of manufacturing the same. The semiconductor package includes: a substrate including a mounting electrode formed on both sides and a wiring; a plurality of first electronic devices mounted on the substrate; a second electronic devices mounted on the substrate; and a via through which the wiring of the substrate and the second electronic devices are connected.
Abstract translation: 这里公开了一种半导体封装及其制造方法。 半导体封装包括:包括形成在两侧的安装电极和布线的基板; 安装在所述基板上的多个第一电子装置; 安装在基板上的第二电子装置; 以及基板和第二电子设备的布线连接的通孔。
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公开(公告)号:US09076660B2
公开(公告)日:2015-07-07
申请号:US14103574
申请日:2013-12-11
Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
Inventor: Tae Hyun Kim , Kwang Soo Kim , Sun Woo Yun , Young Ki Lee , Do Jae Yoo
IPC: H01L23/12 , H01L23/34 , H01L23/053 , H01L23/373
CPC classification number: H01L23/053 , H01L23/3735 , H01L24/73 , H01L2224/32225 , H01L2224/48137 , H01L2224/48227 , H01L2224/48247 , H01L2224/73265 , H01L2924/13034 , H01L2924/1305 , H01L2924/13055 , H01L2924/13091 , H01L2924/19107 , H01L2924/00012 , H01L2924/00 , H01L2924/00014
Abstract: Disclosed herein is a power module package including: a first module configured of a first substrate having one surface and the other surface, a first semiconductor chip mounted on one surface of the first substrate, and a first sealing member formed to cover the first semiconductor chip mounted on one surface of the first substrate from both sides in a thickness direction of the first substrate and expose the other surface of the first substrate; and a case enclosing the first module.
Abstract translation: 本文公开了一种功率模块封装,包括:第一模块,其由具有一个表面和另一个表面的第一衬底构成,安装在第一衬底的一个表面上的第一半导体芯片和形成为覆盖第一半导体芯片的第一密封构件 在第一基板的厚度方向上从两侧安装在第一基板的一个表面上,并露出第一基板的另一个表面; 以及包围第一模块的壳体。
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公开(公告)号:US20150091146A1
公开(公告)日:2015-04-02
申请号:US14288210
申请日:2014-05-27
Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
Inventor: Kyu Hwan Oh , Si Joong Yang , Do Jae Yoo , Young Hoon Kwak
IPC: H01L23/495 , H01L23/31
CPC classification number: H01L23/49568 , H01L23/3107 , H01L23/367 , H01L23/49537 , H01L23/49541 , H01L23/49562 , H01L23/49575 , H01L2224/291 , H01L2224/32245 , H01L2924/1305 , H01L2924/13055 , H01L2924/1815 , H01L2924/18301 , H01L2924/014 , H01L2924/00
Abstract: Disclosed herein is a power semiconductor package. The power semiconductor package according to a preferred embodiment of the present invention includes: a semiconductor device; a circuit pattern formed on the semiconductor device; a molding member burying the semiconductor device and the circuit pattern and formed so as to expose one surface of the circuit pattern; and a heat radiating member adhered to the circuit pattern exposed by the molding member and formed of a non-conductive material.
Abstract translation: 这里公开了功率半导体封装。 根据本发明的优选实施例的功率半导体封装包括:半导体器件; 形成在所述半导体器件上的电路图案; 埋入半导体器件和电路图案并形成以使电路图案的一个表面露出的模制构件; 以及散热构件,其粘附到由所述模制构件露出并由非导电材料形成的所述电路图案。
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17.
公开(公告)号:US20140117408A1
公开(公告)日:2014-05-01
申请号:US13782859
申请日:2013-03-01
Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD
Inventor: Tae Hyun Kim , Bum Seok Suh , Do Jae Yoo , Kwang Soo Kim
IPC: H01L27/07
CPC classification number: H01L24/34 , H01L24/33 , H01L24/36 , H01L24/40 , H01L24/41 , H01L2224/40095 , H01L2224/40137 , H01L2224/83801 , H01L2224/84801 , H01L2924/13034 , H01L2924/1305 , H01L2924/13055 , H01L2924/13091 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2924/00014
Abstract: Disclosed herein is a unit power module including: a first semiconductor chip having one surface on which a 1-1-th electrode and a 1-2-th electrode spaced apart from the 1-1-th electrode are formed and the other surface on which a 1-3-th electrode is formed, a second semiconductor chip having one surface on which a 2-1-th electrode is formed and the other surface on which a 2-2-th electrode is formed, a first metal plate contacting the 1-1-th electrode of the first semiconductor chip and the 2-1-th electrode of the second semiconductor chip, a second metal plate contacting the 1-2-th electrode of the first semiconductor chip and spaced apart from the first metal plate, a third metal plate contacting the 1-3-th electrode of the first semiconductor chip and the 2-2-th electrode of the second semiconductor chip, and a sealing member formed to surround the first metal plate, the second metal plate, and the third metal plate.
Abstract translation: 这里公开了一种单位功率模块,包括:第一半导体芯片,其具有一个表面,其上形成有与第1-1电极间隔开的第1-1电极和第1-2电极,另一个表面在 形成有第1-3电极的第二半导体芯片,形成有第2-1电极的一个表面的第二半导体芯片和形成有第2-2电极的另一表面,第一金属板接触 第一半导体芯片的第1-1电极和第二半导体芯片的第2-1电极,与第一半导体芯片的第1-2电极接触并与第一半导体芯片间隔开的第二金属板 与第一半导体芯片的第1-3电极和第二半导体芯片的第2-2电极接触的第三金属板和形成为围绕第一金属板,第二金属板, 和第三金属板。
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公开(公告)号:US10667419B2
公开(公告)日:2020-05-26
申请号:US15825606
申请日:2017-11-29
Applicant: Samsung Electro-Mechanics Co., Ltd.
Inventor: Do Jae Yoo , Eun Jung Jo , Jae Hyun Lim
Abstract: There are provided an electronic component module in which an external terminal is disposed outwardly from a mold part by a plating process and a manufacturing method thereof. The electronic component module includes a substrate, at least one electronic component mounted on the substrate, a mold part sealing the electronic component, and at least one connection conductor having one end bonded to one surface of the substrate and formed in the mold part so as to penetrate through the mold part. The connection conductor is formed to have a form in which horizontal cross-sectional areas of the connection conductor are gradually reduced toward the substrate and includes at least one step.
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公开(公告)号:US10219380B2
公开(公告)日:2019-02-26
申请号:US14676745
申请日:2015-04-01
Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
Inventor: Do Jae Yoo , Jae Hyun Lim , Kyu Hwan Oh , Jong In Ryu
Abstract: An electronic device module includes a board including external connecting electrodes and mounting electrodes; an electronic device mounted on the mounting electrodes; a molded portion sealing the electronic device; connection conductors having an end bonded to the external connecting electrodes and penetrating through the molded portion; and external terminals bonded to another end of the connection conductors.
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公开(公告)号:US10109595B2
公开(公告)日:2018-10-23
申请号:US15267233
申请日:2016-09-16
Applicant: Samsung Electro-Mechanics Co., Ltd.
Inventor: Do Jae Yoo , Hee Jung Jung , Jong In Ryu , Ki Joo Sim
IPC: H01L23/552 , H01L23/498 , H01L23/31 , H01L25/065 , H01L25/18 , H01L21/48 , H01L21/56
Abstract: A double-sided package module includes a substrate, a first sealing member, a second sealing member, and an extension portion. The substrate includes electronic components positioned on a first surface and a second surface of the substrate. The first sealing member and the second sealing member are positioned on the first surface and the second surface, respectively. The extension portion protrudes from a lateral surface of the substrate into a space between the first sealing member and the second sealing member.
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