公开(公告)号：US11456317B2

公开(公告)日：2022-09-27

申请号：US17023053

申请日：2020-09-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chanho Kim ,  Daeseok Byeon ,  Dongku Kang

IPC: H01L27/11573 ,  H01L27/11582 ,  G11C8/14 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11526 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565

Abstract: A memory device includes a peripheral circuit region comprising a first substrate, a plurality of metal layers over the first substrate, and a first metal pad, a cell region comprising a second substrate, a plurality of gate lines over the second substrate, a plurality of upper interconnection layers in the second substrate, and a second metal pad, wherein the cell region is vertically connected to the peripheral circuit region by the first metal pad and the second metal pad, a common source line between the second substrate and the plurality of gate lines, the common source line comprising a through hole, and a word line cut region extending across the plurality of gate lines and extending through the through hole of the common source line to be connected to a first upper interconnection layer from among the plurality of upper interconnection layers.

公开(公告)号：US20220277792A1

公开(公告)日：2022-09-01

申请号：US17746393

申请日：2022-05-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyunghwa Yun ,  Chanho Kim ,  Pansuk Kwak

IPC: G11C16/08 ,  G11C16/10 ,  H01L27/11582 ,  H01L27/1157 ,  H01L27/11573

Abstract: A memory device including: a memory cell array disposed in a first semiconductor layer, the memory cell array including a plurality of wordlines extended in a first direction and stacked in a second direction substantially perpendicular to the first direction; and a plurality of pass transistors disposed in the first semiconductor layer, wherein a first pass transistor of the plurality of pass transistors is disposed between a first signal line of a plurality of signal lines and a first wordline of the plurality of wordlines, and wherein the plurality of signal lines are arranged at the same level as a common source line.

公开(公告)号：US11270759B2

公开(公告)日：2022-03-08

申请号：US17006990

申请日：2020-08-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chanho Kim ,  Daeseok Byeon ,  Hyunsurk Ryu

IPC: G11C5/06 ,  G11C11/4094 ,  G11C16/08 ,  G11C11/4093 ,  G11C11/408 ,  G06N3/063 ,  G11C16/04

Abstract: A flash memory device includes: first pads; second pads; third pads; a memory cell region including first metal pads and a memory cell array; and a peripheral circuit region including a second metal pads and vertically connected to the memory cell region by the first metal pads and the second metal pads directly. The peripheral circuit region includes a row decoder block; a buffer block storing a command and an address received from an external semiconductor chip through the first pads; a page buffer block connected to the memory cell array through bit lines, connected to the third pads through data lines, and exchanging data signals with the external semiconductor chip through the data lines and the third pads; and a control logic block receiving control signals from the external semiconductor chip through the second pads, and controlling the row decoder block and the page buffer block.

公开(公告)号：US20210065751A1

公开(公告)日：2021-03-04

申请号：US16816476

申请日：2020-03-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jooyong Park ,  Chanho Kim ,  Daeseok Byeon

IPC: G11C5/06 ,  G11C7/18 ,  G11C5/04

Abstract: A memory device includes a first semiconductor chip including a memory cell array disposed on a first substrate, and a first bonding metal on a first uppermost metal layer of the first semiconductor chip, and a second semiconductor chip including circuit devices disposed on a second substrate and a second bonding metal on a second uppermost metal layer of the second semiconductor chip, the circuit devices providing a peripheral circuit operating the memory cell array. The first and second semiconductor chips are electrically connected to each other by the first bonding metal and the second bonding metal in a bonding area. A routing wire electrically connected to the peripheral circuit is disposed in one or both of the first and second uppermost metal layers and is disposed in a non-bonding area in which the first and second semiconductor chips are not electrically connected to each other.

公开(公告)号：US10763278B2

公开(公告)日：2020-09-01

申请号：US16243837

申请日：2019-01-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyunghwa Yun ,  Pansuk Kwak ,  Chanho Kim ,  Junghwa Lee

IPC: H01L27/11582 ,  H01L23/528 ,  H01L23/535 ,  H01L27/11573

Abstract: A semiconductor memory device includes a substrate having a cell array region and a contact region, a stack structure including a plurality of gate electrodes on the cell array region and the contact region, a plurality of cell vertical channel structures extending through the stack structure on the cell array region, and a contact structure disposed beside of the stack structure on a top surface of the substrate and disposed along a line extending from the cell array region toward the contact region. The height of the contact structure on the cell array region is different from the height of the contact structure on the contact region.

公开(公告)号：US11723208B2

公开(公告)日：2023-08-08

申请号：US17695186

申请日：2022-03-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyunghwa Yun ,  Pansuk Kwak ,  Chanho Kim ,  Dongku Kang

IPC: G11C11/00 ,  H10B43/40 ,  G11C16/08 ,  G11C7/18 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

CPC classification number: H10B43/40 ,  G11C7/18 ,  G11C16/08 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

Abstract: A memory device comprises a peripheral circuit region including a first substrate and circuit elements on the first substrate, the circuit elements including a row decoder, and a memory cell region including a cell array region and a cell contact region, wherein the cell array region includes wordlines, stacked on a second substrate on the peripheral circuit region, and channel structures extending in a direction perpendicular to an upper surface of the second substrate and penetrating the wordlines, wherein the cell contact region includes cell contacts connected to the wordlines and on both sides of the cell array region in a first direction parallel to the upper surface of the second substrate, the cell contacts including a first cell contact region and a second cell contact region, the first and second cell contact regions having different lengths to each other in the first direction, wherein each of the first and second cell contact regions includes first pads having different lengths than each other in the first direction, and second pads different from the first pads, wherein the cell contacts are connected to the wordlines in the first pads, wherein the number of the second pads included in the first cell contact region is greater than the number of the second pads included in the second cell contact region, and wherein the memory cell region includes a first metal pad and the peripheral circuit region includes a second metal pad, and the memory cell region and the peripheral circuit region are vertically connected to each other by the first metal pad and the second metal pad.

公开(公告)号：US11664361B2

公开(公告)日：2023-05-30

申请号：US17577647

申请日：2022-01-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chanho Kim ,  Joo-Yong Park ,  Daeseok Byeon

IPC: H01L25/18 ,  H01L23/00

CPC classification number: H01L25/18 ,  H01L24/08 ,  H01L2224/08145 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: A three-dimensional semiconductor memory device, including a peripheral circuit structure including a first metal pad and a cell array structure disposed on the peripheral circuit structure and including a second metal pad. The peripheral circuit structure may include a first substrate including a first peripheral circuit region and a second peripheral circuit region, first contact plugs, second contact plugs, and a first passive device on and electrically connected to the second contact plugs. The cell array structure may include a second substrate disposed on the peripheral circuit structure, the second substrate including a cell array region and a contact region. The cell array structure may further include gate electrodes and cell contact plugs. The first passive device is vertically between the gate electrodes and the second contact plugs and includes a first contact line. The first metal pad and the second metal pad may be connected by bonding manner.

公开(公告)号：US11430806B2

公开(公告)日：2022-08-30

申请号：US16878756

申请日：2020-05-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyunghwa Yun ,  Chanho Kim ,  Dongku Kang

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11573

Abstract: A nonvolatile memory device includes a peripheral circuit including a first active region and a memory block including a second active region on the peripheral circuit. The memory block includes a vertical structure including pairs of a first insulating layer and a first conductive layer, a second insulating layer on the vertical structure, a second conductive layer and a third conductive layer spaced apart from each other on the second insulating layer, first vertical channels and second vertical channels. The second conductive layer and the third conductive layer are connected with a first through via penetrating the vertical structure, the second active region, and a region of the second insulating layer that is exposed between the second conductive layer and the third conductive layer.

公开(公告)号：US11430804B2

公开(公告)日：2022-08-30

申请号：US16809059

申请日：2020-03-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyunghwa Yun ,  Chanho Kim ,  Dongku Kang

IPC: H01L27/11582 ,  H01L27/11565

Abstract: A vertical memory device is provided. The vertical memory device includes gate electrodes formed on a substrate and spaced apart from each other in a first direction substantially perpendicular to an upper surface of the substrate, the gate electrodes including a first gate electrode and a second gate electrode that is interposed between the first gate electrode and the substrate; a channel extending through the gate electrodes in the first direction; an insulating isolation pattern extending through the first gate electrode in the first direction, and spaced apart from the first gate electrode in a second direction substantially parallel to the upper surface of the substrate; and a blocking pattern disposed on an upper surface, a lower surface and a sidewall of each of the gate electrodes, the sidewall of the gate electrodes facing the channel. The insulating isolation pattern directly contacts the first gate electrode.

公开(公告)号：US11348910B2

公开(公告)日：2022-05-31

申请号：US16863736

申请日：2020-04-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chanho Kim ,  Kyunghwa Yun ,  Daeseok Byeon

IPC: H01L25/18 ,  H01L25/065 ,  H01L23/00 ,  G11C16/04 ,  G11C16/08

Abstract: A non-volatile memory device includes a first semiconductor layer having a stair area and a cell area having a memory cell array formed therein, and a second semiconductor layer including a page buffer connected to the memory cell array. The first semiconductor layer includes a plurality of word lines, a ground selection line in a layer on the word lines, a common source line in a layer on the ground selection line, a plurality of vertical pass transistors in the stair area, and a plurality of driving signal lines in the same layer as the common source line. The word lines form a stair shape in the stair area, and each of the vertical pass transistors is connected between a corresponding one of the word lines and a corresponding one of the driving signal lines.