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    Integrated circuit device
    13.
    发明授权
    Integrated circuit device 有权

    公开(公告)号：US12237383B2

    公开(公告)日：2025-02-25

    申请号：US17404078

    申请日：2021-08-17

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Dohee Kim ,  Gyeom Kim ,  Jinbum Kim ,  Jaemun Kim ,  Seunghun Lee

    IPC: H01L29/417 ,  H01L27/088 ,  H01L29/78

    Abstract: An integrated circuit (IC) device includes a fin-type active region extending in a first lateral direction on a substrate, a gate line extending in a second lateral direction on the fin-type active region, an insulating spacer covering a sidewall of the gate line, a source/drain region at a position adjacent to the gate line, a metal silicide film covering a top surface of the source/drain region, and a source/drain contact apart from the gate line with the insulating spacer therebetween in the first lateral direction. The source/drain contact includes a bottom contact segment being in contact with a top surface of the metal silicide film and an upper contact segment integrally connected to the bottom contact segment. A width of the bottom contact segment is greater than a width of at least a portion of the upper contact segment in the first lateral direction.

    SEMICONDUCTOR DEVICE
    14.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20250040188A1

    公开(公告)日：2025-01-30

    申请号：US18588322

    申请日：2024-02-27

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Yang Xu ,  Gyeom Kim ,  Pankwi Park ,  Ryong Ha ,  Yoon Heo

    IPC: H01L29/423 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

    Abstract: A semiconductor device includes a substrate; an active region extending in a first, horizontal, direction on the substrate, and including a first active pattern at a first height above a bottom surface of the substrate in a vertical direction and having a first width in a second, horizontal, direction, a second active pattern having a second width in the second direction different from the first width, and a transition active pattern connecting the first active pattern to the second active pattern; gate structures intersecting the active region each gate structure extending in the second direction across the substrate; source/drain regions disposed on sides of the gate structures, and including a first source/drain region disposed on the first active pattern, a second source/drain region disposed on the second active pattern, and a transition source/drain region disposed on the transition active pattern. Each of the source/drain regions is disposed on the active region and includes a first epitaxial layer having a recessed upper surface and a second epitaxial layer disposed on the first epitaxial layer, at a second height above a bottom surface of the substrate in a vertical direction, a first sidewall thickness of the first epitaxial layer of the first source/drain region in the first direction is different from a second sidewall thickness of the first epitaxial layer of the second source/drain region in the first direction, at the second height, thicknesses of opposing sidewalls of the first epitaxial layer of the transition source/drain region in the first direction are different, and a vertical level of a lowermost end of the second epitaxial layer of the first source/drain region, a vertical level of a lowermost end of the second epitaxial layer of the second source/drain region, and a vertical level of a lowermost end of the second epitaxial layer of the transition source/drain region are different from each other.

    Integrated circuit device
    16.
    发明授权
    Integrated circuit device 有权

    公开(公告)号：US12113108B2

    公开(公告)日：2024-10-08

    申请号：US17472926

    申请日：2021-09-13

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Dohee Kim ,  Gyeom Kim ,  Jinbum Kim ,  Haejun Yu ,  Kyungin Choi ,  Kihyun Hwang ,  Seunghun Lee

    IPC: H01L29/41 ,  H01L27/088 ,  H01L29/417

    CPC classification number: H01L29/41775 ,  H01L27/0886

    Abstract: An integrated circuit device includes a plurality of gate structures each including a gate line extending on a fin-type active region and insulation spacers on sidewalls of the gate line; a source/drain contact between first and second gate structures, and having opposing sides that are asymmetric in the first horizontal direction; and an insulation liner on sidewalls of the source/drain contact. The source/drain contact includes a lower contact portion and an upper contact portion having a horizontal extension that extends on an upper corner of the first gate structure, the insulation liner includes a first local region between the upper corner and the horizontal extension and a second local region that is farther from the substrate than the first local region, and a thickness of the first local region is greater than that of the second local region.

    Semiconductor Device
    17.
    发明申请
    Semiconductor Device 有权

    公开(公告)号：US20230011153A1

    公开(公告)日：2023-01-12

    申请号：US17672233

    申请日：2022-02-15

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Dong Woo Kim ,  Gyeom Kim ,  Jin Bum Kim ,  Dong Suk Shin ,  Sang Moon Lee

    IPC: H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/417

    Abstract: A semiconductor device comprises an active pattern on a substrate; a plurality of nanosheets spaced apart from each other; a gate electrode surrounding each of the nanosheets; a field insulating layer surrounding side walls of the active pattern; an interlayer insulating layer on the field insulating layer; a source/drain region comprising a first doping layer on the active pattern, a second doping layer on the first doping layer, and a capping layer forming side walls adjacent to the interlayer insulating layer; a source/drain contact electrically connected to, and on, the source/drain region, and a silicide layer between the source/drain region and the source/drain contact which contacts contact with the second doping layer and extends to an upper surface of the source/drain region. The capping layer extends from an upper surface of the field insulating layer to the upper surface of the source/drain region along side walls of the silicide layer.

    INTEGRATED CIRCUIT DEVICE
    18.
    发明申请
    INTEGRATED CIRCUIT DEVICE 有权

    公开(公告)号：US20220246738A1

    公开(公告)日：2022-08-04

    申请号：US17472926

    申请日：2021-09-13

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Dohee Kim ,  Gyeom Kim ,  Jinbum Kim ,  Haejun Yu ,  Kyungin Choi ,  Kihyun Hwang ,  Seunghun Lee

    IPC: H01L29/417 ,  H01L27/088

    Abstract: An integrated circuit device includes a plurality of gate structures each including a gate line extending on a fin-type active region and insulation spacers on sidewalls of the gate line; a source/drain contact between first and second gate structures, and having opposing sides that are asymmetric in the first horizontal direction; and an insulation liner on sidewalls of the source/drain contact. The source/drain contact includes a lower contact portion and an upper contact portion having a horizontal extension that extends on an upper corner of the first gate structure, the insulation liner includes a first local region between the upper corner and the horizontal extension and a second local region that is farther from the substrate than the first local region, and a thickness of the first local region is greater than that of the second local region.

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