公开(公告)号：US20240213349A1

公开(公告)日：2024-06-27

申请号：US18396258

申请日：2023-12-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sanghyun JO ,  Yunseong LEE ,  Hyangsook LEE ,  Dukhyun CHOE ,  Jinseong HEO

IPC: H01L29/51 ,  H01L21/28 ,  H01L29/423 ,  H01L29/78 ,  H10B51/20 ,  H10B53/20

CPC classification number: H01L29/516 ,  H01L29/40111 ,  H01L29/42392 ,  H01L29/78391 ,  H01L29/7851 ,  H10B51/20 ,  H10B53/20

Abstract: An electronic device and an electronic apparatus including the electronic device are provided. The electronic device includes a conductive material layer, and a ferroelectric layer covering the conductive material layer. The ferroelectric layer includes a first oxide layer including a first component, and a second oxide layer including hafnium and a second component and having a thickness that is twice or more than a thickness of the first oxide layer.

公开(公告)号：US20240194761A1

公开(公告)日：2024-06-13

申请号：US18531078

申请日：2023-12-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sanghyun JO ,  Hyangsook LEE ,  Eunha LEE ,  Jinseong HEO

IPC: H01L29/51 ,  H01L29/49 ,  H01L29/78 ,  H10B51/20 ,  H10B53/30

CPC classification number: H01L29/516 ,  H01L29/4908 ,  H01L29/78391 ,  H10B51/20 ,  H10B53/30 ,  H01L29/775

Abstract: Provided as an electronic device and an electronic apparatus including the electronic device. The electronic device includes a conductive material layer, a mixed material layer covering the conductive material layer, and an electrode layer covering the mixed material layer. The mixed material layer includes an orthorhombic crystal phase and a tetragonal crystal phase mixed therein such that a ferroelectric material and an anti-ferroelectric material coexist therein.

公开(公告)号：US20230116309A1

公开(公告)日：2023-04-13

申请号：US18060140

申请日：2022-11-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinseong HEO ,  Sangwook KIM ,  Yunseong LEE ,  Sanghyun JO ,  Hyangsook LEE

IPC: H01L29/78 ,  H01L29/40 ,  H01L29/51

Abstract: Provided are an electronic device and a method of manufacturing the same. The electronic device includes a ferroelectric crystallization layer between a substrate and a gate electrode and a crystallization prevention layer between the substrate and the ferroelectric crystallization layer. The ferroelectric crystallization layer is at least partially crystallized and includes a dielectric material having ferroelectricity or anti-ferroelectricity. Also, the crystallization prevention layer prevents crystallization in the ferroelectric crystallization layer from being spread toward the substrate.

公开(公告)号：US20230068904A1

公开(公告)日：2023-03-02

申请号：US17876979

申请日：2022-07-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinseong HEO ,  Yunseong LEE ,  Hyangsook LEE ,  Sanghyun JO ,  Seunggeol NAM ,  Taehwan MOON ,  Hagyoul BAE ,  Eunha LEE ,  Junho LEE

IPC: H01L29/78 ,  H01L29/51 ,  H01L29/10

Abstract: An electronic device includes: a substrate including a source, a drain, and a channel between the source and the drain; a gate electrode arranged above the substrate and facing the channel, the gate electrode being apart from the channel in a first direction; and a ferroelectric thin film structure between the channel and the gate electrode, the ferroelectric thin film structure including a first ferroelectric layer, a crystallization barrier layer including a dielectric material, and a second ferroelectric layer, which are sequentially arranged from the channel in the first direction. The average of sizes of crystal grains of the first ferroelectric layer may be less than or equal to the average of sizes of crystal grains of the second ferroelectric layer, and owing to small crystal grains, dispersion of performance may be improved.

公开(公告)号：US20220254870A1

公开(公告)日：2022-08-11

申请号：US17344475

申请日：2021-06-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyangsook LEE ,  Junghwa KIM ,  Eunha LEE ,  Jeonggyu SONG ,  Jooho LEE ,  Myoungho JEONG

IPC: H01L49/02 ,  H01L29/08

Abstract: Provided are dielectric thin-film structures and electronic devices including the same. The dielectric thin-film structure includes a substrate, and a dielectric layer provided on the substrate. The dielectric layer including a tetragonal crystal structure, and crystal grains including a proportion of the crystal grains preferentially oriented such that at least one of a , , or direction of a crystal lattice is parallel to or forms an angle of less than 45 degrees an out-of-plane orientation.

公开(公告)号：US20240266418A1

公开(公告)日：2024-08-08

申请号：US18635385

申请日：2024-04-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sanghyun JO ,  Jinseong HEO ,  Hyangsook LEE ,  Sangwook KIM ,  Yunseong LEE

IPC: H01L29/51 ,  H01L21/02

CPC classification number: H01L29/517 ,  H01L21/02181 ,  H01L21/02194 ,  H01L21/022 ,  H01L21/02356 ,  H01L28/40 ,  H01L29/516 ,  H01L29/513

Abstract: Disclosed herein is a thin film structure, including a first conductive layer on a dielectric layer including a plurality of layers. Each of the plurality of layers includes a dopant layer containing a dopant A and a HfO2layer to form a compound of HfxA1-xOz (0

公开(公告)号：US20240038891A1

公开(公告)日：2024-02-01

申请号：US18487275

申请日：2023-10-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinseong HEO ,  Sangwook KIM ,  Yunseong LEE ,  Sanghyun JO ,  Hyangsook LEE

IPC: H01L29/78 ,  H01L29/40 ,  H01L29/51

CPC classification number: H01L29/78391 ,  H01L29/401 ,  H01L29/516

Abstract: Provided are an electronic device and a method of manufacturing the same. The electronic device includes a ferroelectric crystallization layer between a substrate and a gate electrode and a crystallization prevention layer between the substrate and the ferroelectric crystallization layer. The ferroelectric crystallization layer is at least partially crystallized and includes a dielectric material having ferroelectricity or anti-ferroelectricity. Also, the crystallization prevention layer prevents crystallization in the ferroelectric crystallization layer from being spread toward the substrate.

公开(公告)号：US20230282389A1

公开(公告)日：2023-09-07

申请号：US17897519

申请日：2022-08-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangjun LEE ,  Gabjin NAM ,  Eunha LEE ,  Hyangsook LEE ,  Bongjin KUH ,  Junghwa KIM

IPC: H01B3/12 ,  H01B3/10 ,  H01L29/51 ,  H01L29/49 ,  H01L49/02

CPC classification number: H01B3/12 ,  H01B3/10 ,  H01L29/516 ,  H01L29/517 ,  H01L29/4908 ,  H01L28/40 ,  H01L29/785

Abstract: A thin-film structure and a semiconductor device including the same are provided. The thin-film structure includes: a base layer; and a dielectric layer on the base layer, the dielectric layer including crystals including a (0≤x≤1) crystal orientation in an out-of-plane direction of the base layer and having an orthorhombic crystal structure of an oIV phase (space group: Pmn21).

公开(公告)号：US20230154973A1

公开(公告)日：2023-05-18

申请号：US18154218

申请日：2023-01-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyangsook LEE ,  Junghwa KIM ,  Eunha LEE ,  Jeonggyu SONG ,  Jooho LEE ,  Myoungho JEONG

IPC: H01L29/08 ,  H01L21/02

CPC classification number: H01L28/55 ,  H01L21/02433 ,  H01L21/02189 ,  H01L29/0847 ,  H01L21/02609 ,  H01L21/02516 ,  H01L21/02181 ,  H01L28/60

Abstract: Provided are dielectric thin-film structures and electronic devices including the same. The dielectric thin-film structure includes a substrate, and a dielectric layer provided on the substrate. The dielectric layer including a tetragonal crystal structure, and crystal grains including a proportion of the crystal grains preferentially oriented such that at least one of a , , or direction of a crystal lattice is parallel to or forms an angle of less than 45 degrees an out-of-plane orientation.

公开(公告)号：US20220140067A1

公开(公告)日：2022-05-05

申请号：US17334030

申请日：2021-05-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeonggyu SONG ,  Younsoo KIM ,  Haeryong KIM ,  Boeun PARK ,  Eunha LEE ,  Jooho LEE ,  Hyangsook LEE ,  Yong-Hee CHO ,  Eunae CHO

IPC: H01L49/02 ,  H01L29/08

Abstract: A semiconductor device includes a lower electrode; an upper electrode disposed to be spaced apart from the lower electrode; and a dielectric layer disposed between the lower electrode and the upper electrode, and including a first metal oxide region, a second metal oxide region, and a third metal oxide region.