公开(公告)号：US20240413086A1

公开(公告)日：2024-12-12

申请号：US18387997

申请日：2023-11-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： JINBUM KIM ,  GUIFU YANG ,  Suk Yang ,  SANGMOON LEE ,  SUNGUK JANG ,  SUNG-HWAN JANG ,  Wonhee Choi

IPC: H01L23/528 ,  H01L29/06 ,  H01L29/08 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

Abstract: Provided is a semiconductor device including a lower pattern layer including a first semiconductor material; a first conductivity-type doped pattern layer disposed on the lower pattern layer and including a semiconductor material doped with a first conductivity-type impurity; a source/drain pattern disposed on the first conductivity-type doped pattern layer and including a semiconductor material doped with a second conductivity-type impurity different from the first conductivity-type impurity; a channel pattern including semiconductor patterns connected between the source/drain patterns, stacked apart from each other, and including a second semiconductor material different from the first semiconductor material; and a gate pattern disposed on the first conductivity-type doped pattern layer and between the source/drain patterns, and surrounding the channel pattern.

公开(公告)号：US20220344469A1

公开(公告)日：2022-10-27

申请号：US17862453

申请日：2022-07-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： JINBUM KIM ,  DAHYE KIM ,  SEOKHOON KIM ,  JAEMUN KIM ,  ILGYOU SHIN ,  Haejun YU ,  KYUNGIN CHOI ,  KIHYUN HWANG ,  SANGMOON LEE ,  SEUNG HUN LEE ,  KEUN HWI CHO

IPC: H01L29/08 ,  H01L29/165 ,  H01L29/78 ,  H01L21/8238 ,  H01L29/423 ,  H01L29/66 ,  H01L27/092 ,  H01L29/786

Abstract: A semiconductor device includes an active pattern on a substrate, a pair of source/drain patterns on the active pattern, a channel pattern between the pair of source/drain patterns, the channel pattern including semiconductor patterns stacked to be spaced apart from each other, and a gate electrode crossing the channel pattern and extending in a first direction. One of the pair of source/drain patterns includes a first semiconductor layer and a second semiconductor layer thereon. The first semiconductor layer is in contact with a first semiconductor pattern, which is one of the stacked semiconductor patterns. The largest widths of the first semiconductor pattern, the first semiconductor layer, and the second semiconductor layer in the first direction are a first width, a second width, a third width, respectively, and the second width is larger than the first width and smaller than the third width.

公开(公告)号：US20220246728A1

公开(公告)日：2022-08-04

申请号：US17514379

申请日：2021-10-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： DAHYE KIM ,  JINBUM KIM ,  JAEMUN KIM ,  SANGMOON LEE ,  SEUNG HUN LEE

IPC: H01L29/165 ,  H01L27/092 ,  H01L29/786 ,  H01L29/417 ,  H01L29/423 ,  H01L29/06

Abstract: A semiconductor device includes a substrate including a peripheral region, a first active pattern on the peripheral region, the first active pattern having an upper portion including first semiconductor patterns and second semiconductor patterns, which are alternately stacked, a first gate electrode intersecting the first active pattern, a pair of first source/drain patterns provided at both sides of the first gate electrode, respectively, a first capping layer on the first active pattern, a second capping layer on the first capping layer, and a first gate insulating layer between the second capping layer and the first gate electrode. The first capping layer is between a sidewall of the first active pattern and the second capping layer. A concentration of germanium (Ge) of the first capping layer is greater than a concentration of germanium of the second capping layer.

公开(公告)号：US20220059534A1

公开(公告)日：2022-02-24

申请号：US17231502

申请日：2021-04-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： KYUNGIN CHOI ,  JINBUM KIM ,  Haejun YU ,  SEUNG HUN LEE

IPC: H01L27/092 ,  H01L29/66 ,  H01L29/78 ,  H01L29/417

Abstract: A semiconductor device includes: a first active pattern on a substrate and including a first active fin and a second active fin; a device isolation layer defining the first active pattern; a gate electrode crossing the first active pattern; a first source/drain pattern and a second source/drain pattern on the first active fin and the second active fin, respectively; an inner fin spacer between the first and second source/drain patterns; and a buffer layer between the first and second active fins, wherein the inner fin spacer includes: a first inner spacer portion contacting the first source/drain pattern; a second inner spacer portion contacting the second source/drain pattern; and an inner extended portion extending from the first and second inner spacer portions, wherein the inner extended portion is between the first and second active fins, wherein the buffer layer has a dielectric constant higher than that of the inner fin spacer.

公开(公告)号：US20210343841A1

公开(公告)日：2021-11-04

申请号：US17088011

申请日：2020-11-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： ILGYOU SHIN ,  MINYI KIM ,  MYUNG GIL KANG ,  JINBUM KIM ,  SEUNG HUN LEE ,  KEUN HWI CHO

IPC: H01L29/15 ,  H01L29/10 ,  H01L29/417 ,  H01L29/78

Abstract: A semiconductor device includes; a substrate including a first region and a second region, a first active pattern extending upward from the first region, a first superlattice pattern on the first active pattern, a first active fin centrally disposed on the first active pattern, a first gate electrode disposed on the first active fin, and first source/drain patterns disposed on opposing sides of the first active fin and on the first active pattern. The first superlattice pattern includes at least one first semiconductor layer and at least one first blocker-containing layer, and the first blocker-containing layer includes at least one of oxygen, carbon, fluorine and nitrogen.

公开(公告)号：US20230420518A1

公开(公告)日：2023-12-28

申请号：US18088890

申请日：2022-12-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： GYEOM KIM ,  DAHYE KIM ,  JINBUM KIM ,  KYUNGBIN CHUN

IPC: H01L29/08 ,  H01L29/06 ,  H01L29/161 ,  H01L29/423 ,  H01L29/775 ,  H01L21/02 ,  H01L29/66

CPC classification number: H01L29/0847 ,  H01L29/0673 ,  H01L29/161 ,  H01L29/42392 ,  H01L29/775 ,  H01L21/02532 ,  H01L29/66545 ,  H01L29/66439

Abstract: An integrated circuit (IC) device includes a fin-type active region, a channel region on the fin-type active region, a gate line surrounding the channel region, an outer insulating spacer covering a sidewall of the gate line, a source/drain region on the fin-type active region, wherein the source/drain region includes a buffer layer including a portion in contact with the channel region and a portion in contact with the fin-type active region, the buffer layer including an edge buffer portion having a smaller thickness than other portions thereof at a position adjacent to the outer insulating spacer, a local buffer pattern including a wedge portion, the wedge portion filling a space defined by the edge buffer portion and the outer insulating spacer, and a main body layer in contact with each of the buffer layer and the local buffer pattern.

公开(公告)号：US20220416086A1

公开(公告)日：2022-12-29

申请号：US17711914

申请日：2022-04-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： HYOJIN KIM ,  SANGMOON LEE ,  JINBUM KIM ,  YONGJUN NAM

IPC: H01L29/786 ,  H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L21/02 ,  H01L21/265 ,  H01L21/8238 ,  H01L29/66

Abstract: A semiconductor device includes; a first fin vertically protruding from a substrate and extending in a first horizontal direction, a second fin vertically protruding from the substrate, an isolation layer contacting side surfaces of the first fin and the second fin, a first lower barrier layer on the first fin, a second lower barrier layer on the second fin, source/drain regions spaced apart in the first horizontal direction on the first lower barrier layer, channel layers disposed between the source/drain regions and vertically spaced apart on the first barrier layer, a gate structure intersecting the first lower barrier layer, surrounding each of the channel layers, and extending in a second horizontal direction, an upper barrier layer on the second lower barrier layer, and first semiconductor layers and second semiconductor layers stacked on the upper barrier layer.

公开(公告)号：US20220416082A1

公开(公告)日：2022-12-29

申请号：US17585686

申请日：2022-01-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： SUJIN JUNG ,  JINBUM KIM ,  DAHYE KIM ,  INGYU JANG ,  DONGSUK SHIN

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/08

Abstract: Disclosed are a semiconductor device and a method of fabricating the same, the semiconductor device including an active pattern on a substrate, a source/drain pattern on the active pattern, a channel pattern on the active pattern, connected to the source/drain pattern, and including stacked semiconductor patterns, a gate electrode extending in a first direction and crossing the channel pattern, and a gate insulating layer between the gate electrode and the channel pattern. The source/drain pattern includes first and second semiconductor layers, the first semiconductor layer including a center portion including a second outer side surface in contact with the gate insulating layer and an edge portion adjacent to a side of the center portion and including a first outer side surface in contact with the gate insulating layer. The second outer side surface is further recessed toward the second semiconductor layer, compared with the first outer side surface.

公开(公告)号：US20220336214A1

公开(公告)日：2022-10-20

申请号：US17853990

申请日：2022-06-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： GYEOM KIM ,  Dongwoo Kim ,  Jihye Yi ,  JINBUM KIM ,  Sangmoon Lee ,  Seunghun Lee

IPC: H01L21/02 ,  H01L21/285 ,  H01L21/768 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/08 ,  H01L29/165 ,  H01L29/417 ,  H01L23/485 ,  H01L29/78 ,  H01L29/786 ,  H01L29/423 ,  H01L29/06 ,  H01L29/775

Abstract: A semiconductor device is provided. The semiconductor device includes: an active region on a semiconductor substrate; a channel region on the active region; a source/drain region adjacent to the channel region on the active region; a gate structure overlapping the channel region, on the channel region; a contact structure on the source/drain region; a gate spacer between the contact structure and the gate structure; and a contact spacer surrounding a side surface of the contact structure. The source/drain region includes a first epitaxial region having a recessed surface and a second epitaxial region on the recessed surface of the first epitaxial region, and the second epitaxial region includes an extended portion, extended from a portion overlapping the contact structure in a vertical direction, in a horizontal direction and overlapping the contact spacer in the vertical direction.

公开(公告)号：US20210367036A1

公开(公告)日：2021-11-25

申请号：US17128153

申请日：2020-12-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： JINBUM KIM ,  DAHYE KIM ,  SEOKHOON KIM ,  JAEMUN KIM ,  ILGYOU SHIN ,  Haejun YU ,  KYUNGIN CHOI ,  KIHYUN HWANG ,  SANGMOON LEE ,  SEUNG HUN LEE ,  KEUN HWI CHO

IPC: H01L29/08 ,  H01L29/165 ,  H01L29/78 ,  H01L27/092 ,  H01L29/423 ,  H01L29/66 ,  H01L21/8238

Abstract: A semiconductor device includes an active pattern on a substrate, a pair of source/drain patterns on the active pattern, a channel pattern between the pair of source/drain patterns, the channel pattern including semiconductor patterns stacked to be spaced apart from each other, and a gate electrode crossing the channel pattern and extending in a first direction. One of the pair of source/drain patterns includes a first semiconductor layer and a second semiconductor layer thereon. The first semiconductor layer is in contact with a first semiconductor pattern, which is one of the stacked semiconductor patterns. The largest widths of the first semiconductor pattern, the first semiconductor layer, and the second semiconductor layer in the first direction are a first width, a second width, a third width, respectively, and the second width is larger than the first width and smaller than the third width.