公开(公告)号：US09202819B2

公开(公告)日：2015-12-01

申请号：US14493849

申请日：2014-09-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Juyul Lee ,  Bumsu Kim ,  Kwangmin Park ,  Hyun Park ,  Jae-young Ahn ,  Dongchul Yoo ,  Jongsik Chun ,  Kihyun Hwang

IPC: H01L27/105 ,  H01L27/115 ,  H01L29/792

CPC classification number: H01L27/11582 ,  H01L27/1052 ,  H01L29/7926

Abstract: A three-dimensional (3D) semiconductor memory device includes an electrode separation pattern, a stack structure, a data storage layer, and a channel structure. The electrode separation pattern is disposed on a substrate. A stack structure is disposed on a sidewall of the electrode separation pattern. The stack structure includes a corrugated sidewall opposite to the sidewall of the electrode separation pattern. The sidewall of the electrode separation pattern is vertical to the substrate. A data storage layer is disposed on the corrugated sidewall. A channel structure is disposed on the charge storage layer.

Abstract translation: 三维（3D）半导体存储器件包括电极分离图案，堆叠结构，数据存储层和沟道结构。 电极分离图案设置在基板上。 堆叠结构设置在电极分离图案的侧壁上。 堆叠结构包括与电极分离图案的侧壁相对的波纹状侧壁。 电极分离图案的侧壁垂直于基板。 数据存储层设置在波纹侧壁上。 通道结构设置在电荷存储层上。

公开(公告)号：US09184302B2

公开(公告)日：2015-11-10

申请号：US13765213

申请日：2013-02-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chanjin Park ,  Kihyun Hwang ,  Dongchul Yoo ,  Junkyu Yang ,  Gyungjin Min ,  Yoochul Kong ,  Hanmei Choi

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L29/788 ,  H01L27/115 ,  H01L29/66 ,  H01L29/792 ,  H01L23/538

CPC classification number: H01L29/788 ,  H01L23/5384 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11578 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/792 ,  H01L29/7926 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Provided is a three dimensional semiconductor device. The device may include mold layers vertically and sequentially stacked, a conductive pattern between the stacked mold layers, a plugging pattern vertically penetrating the stacked mold layers, an intermediate pattern between the conductive pattern and the plugging pattern, and protective layer patterns between the mold layers and the plugging pattern, wherein the protective layer patterns are separated by the intermediate pattern.

Abstract translation: 提供三维半导体器件。 该装置可以包括垂直和顺序堆叠的模具层，堆叠的模具层之间的导电图案，垂直穿过堆叠的模具层的插入图案，导电图案和插入图案之间的中间图案，以及模具层之间的保护层图案 和封堵图案，其中保护层图案由中间图案分离。

公开(公告)号：US20130146961A1

公开(公告)日：2013-06-13

申请号：US13765213

申请日：2013-02-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chanjin Park ,  Kihyun Hwang ,  Dongchul Yoo ,  Junkyu Yang ,  Gyungjin Min ,  Yoochul Kong ,  Hanmei Choi

IPC: H01L29/788 ,  H01L29/792 ,  H01L23/538

CPC classification number: H01L29/788 ,  H01L23/5384 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11578 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/792 ,  H01L29/7926 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Provided is a three dimensional semiconductor device. The device may include mold layers vertically and sequentially stacked, a conductive pattern between the stacked mold layers, a plugging pattern vertically penetrating the stacked mold layers, an intermediate pattern between the conductive pattern and the plugging pattern, and protective layer patterns between the mold layers and the plugging pattern, wherein the protective layer patterns are separated by the intermediate pattern.

Abstract translation: 提供三维半导体器件。 该装置可以包括垂直和顺序堆叠的模具层，堆叠的模具层之间的导电图案，垂直穿过堆叠的模具层的插入图案，导电图案和插入图案之间的中间图案，以及模具层之间的保护层图案 和封堵图案，其中保护层图案由中间图案分离。

公开(公告)号：USRE50280E1

公开(公告)日：2025-01-21

申请号：US17840850

申请日：2022-06-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jingyun Kim ,  Myoungbum Lee ,  Kihyun Hwang

IPC: H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10

Abstract: Semiconductor memory devices and methods of forming semiconductor memory devices are provided. The methods may include forming insulation layers and cell gate layers that are alternately stacked on a substrate, forming an opening by successively patterning through the cell gate layers and the insulation layers, and forming selectively conductive barriers on sidewalls of the cell gate layers in the opening.

公开(公告)号：US20230163182A1

公开(公告)日：2023-05-25

申请号：US18094484

申请日：2023-01-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kwang Soo Seol ,  Chanjin Park ,  Kihyun Hwang ,  Hanmei Choi ,  Sunghoi Hur ,  Wansik Hwang ,  Toshiro Nakanishi ,  Kwangmin Park ,  Juyul Lee

IPC: H01L29/423 ,  H01L21/3213 ,  H01L27/06 ,  H10B41/20 ,  H10B41/27 ,  H10B43/20 ,  H10B43/27 ,  H01L29/792 ,  H01L29/51

CPC classification number: H01L29/42348 ,  H01L21/32137 ,  H01L27/0688 ,  H10B41/20 ,  H10B41/27 ,  H10B43/20 ,  H10B43/27 ,  H01L29/792 ,  H01L29/511 ,  H01L29/517 ,  H01L2924/0002

Abstract: Three-dimensional semiconductor memory devices and methods of fabricating the same. The three-dimensional semiconductor devices include an electrode structure with sequentially-stacked electrodes disposed on a substrate, semiconductor patterns penetrating the electrode structure, and memory elements including a first pattern and a second pattern interposed between the semiconductor patterns and the electrode structure, the first pattern vertically extending to cross the electrodes and the second pattern horizontally extending to cross the semiconductor patterns.

公开(公告)号：US11588032B2

公开(公告)日：2023-02-21

申请号：US17129667

申请日：2020-12-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kwang Soo Seol ,  Chanjin Park ,  Kihyun Hwang ,  Hanmei Choi ,  Sunghoi Hur ,  Wansik Hwang ,  Toshiro Nakanishi ,  Kwangmin Park ,  Juyul Lee

IPC: H01L29/51 ,  H01L29/423 ,  H01L21/3213 ,  H01L27/06 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11578 ,  H01L29/792 ,  H01L27/11582

Abstract: Three-dimensional semiconductor memory devices and methods of fabricating the same. The three-dimensional semiconductor devices include an electrode structure with sequentially-stacked electrodes disposed on a substrate, semiconductor patterns penetrating the electrode structure, and memory elements including a first pattern and a second pattern interposed between the semiconductor patterns and the electrode structure, the first pattern vertically extending to cross the electrodes and the second pattern horizontally extending to cross the semiconductor patterns.

公开(公告)号：US20230044895A1

公开(公告)日：2023-02-09

申请号：US17969022

申请日：2022-10-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kwang Soo Seol ,  Chanjin Park ,  Kihyun Hwang ,  Hanmei Choi ,  Sunghoi Hur ,  Wansik Hwang ,  Toshiro Nakanishi ,  Kwangmin Park ,  Juyul Lee

IPC: H01L29/423 ,  H01L21/3213 ,  H01L27/06 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11578 ,  H01L29/792 ,  H01L27/11582 ,  H01L29/51

Abstract: Three-dimensional semiconductor memory devices and methods of fabricating the same. The three-dimensional semiconductor devices include an electrode structure with sequentially-stacked electrodes disposed on a substrate, semiconductor patterns penetrating the electrode structure, and memory elements including a first pattern and a second pattern interposed between the semiconductor patterns and the electrode structure, the first pattern vertically extending to cross the electrodes and the second pattern horizontally extending to cross the semiconductor patterns.

公开(公告)号：US20210111260A1

公开(公告)日：2021-04-15

申请号：US17129667

申请日：2020-12-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kwang Soo Seol ,  Chanjin Park ,  Kihyun Hwang ,  Hanmei Choi ,  Sunghoi Hur ,  Wansik Hwang ,  Toshiro Nakanishi ,  Kwangmin Park ,  Juyul Lee

IPC: H01L29/423 ,  H01L21/3213 ,  H01L27/06 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11578 ,  H01L29/792 ,  H01L27/11582 ,  H01L29/51

Abstract: Three-dimensional semiconductor memory devices and methods of fabricating the same. The three-dimensional semiconductor devices include an electrode structure with sequentially-stacked electrodes disposed on a substrate, semiconductor patterns penetrating the electrode structure, and memory elements including a first pattern and a second pattern interposed between the semiconductor patterns and the electrode structure, the first pattern vertically extending to cross the electrodes and the second pattern horizontally extending to cross the semiconductor patterns.

公开(公告)号：US20200258994A1

公开(公告)日：2020-08-13

申请号：US16859437

申请日：2020-04-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kwang Soo Seol ,  Chanjin Park ,  Kihyun Hwang ,  Hanmei Choi ,  Sunghoi Hur ,  Wansik Hwang ,  Toshiro Nakanishi ,  Kwangmin Park ,  Juyul Lee

IPC: H01L29/423 ,  H01L29/51 ,  H01L27/11582 ,  H01L29/792 ,  H01L27/11578 ,  H01L27/11556 ,  H01L27/11551 ,  H01L27/06 ,  H01L21/3213

Abstract: Three-dimensional semiconductor memory devices and methods of fabricating the same. The three-dimensional semiconductor devices include an electrode structure with sequentially-stacked electrodes disposed on a substrate, semiconductor patterns penetrating the electrode structure, and memory elements including a first pattern and a second pattern interposed between the semiconductor patterns and the electrode structure, the first pattern vertically extending to cross the electrodes and the second pattern horizontally extending to cross the semiconductor patterns.

公开(公告)号：US10658375B2

公开(公告)日：2020-05-19

申请号：US15975861

申请日：2018-05-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gukhyon Yon ,  Dongwoo Kim ,  Kihyun Hwang ,  Dongkyum Kim ,  Dongchul Yoo

IPC: H01L27/11582 ,  H01L27/11573 ,  H01L27/24 ,  H01L27/11578 ,  H01L27/11556 ,  H01L27/11575 ,  H01L45/00

Abstract: A three-dimensional semiconductor memory device includes a peripheral circuit structure on a substrate, a horizontal active layer on the peripheral circuit structure, stacks provided on the horizontal active layer to include a plurality of electrodes, a vertical structure vertically penetrating the stacks, a common source region between ones of the stacks and in the horizontal active layer, and pick-up regions in the horizontal active layer. The horizontal active layer includes first, second, and third active semiconductor layers sequentially stacked on the peripheral circuit structure. The first and third active semiconductor layers are doped to have high and low impurity concentrations, respectively, and the second active semiconductor layer includes an impurity diffusion restraining material.