公开(公告)号：US20210104280A1

公开(公告)日：2021-04-08

申请号：US16593393

申请日：2019-10-04

Applicant: SanDisk Technologies LLC

Inventor： Sung-Chul Lee ,  Ching-Huang Lu ,  Henry Chin ,  Changyuan Chen

IPC: G11C16/16 ,  G11C16/34 ,  G11C16/04

Abstract: Method for performing an erase program operation. Various methods include: erasing a block of cells by: applying a program pulse to a block of memory elements in the three-dimensional memory that programs the block of memory elements to a level below an erase verify level, where the three-dimensional memory comprises memory elements stacked vertically; performing a verify step to verify voltage levels of a group of memory elements; determining that a memory element of the group is outside of a threshold window defined between the erase verify level and a compact erase threshold amount; and applying a second program pulse to the memory element. Where erasing the block of memory elements creates an erased block, where a width of the voltage distribution of the erased memory elements in the erased block is the same as or below a width of a voltage distribution associated with programmed memory elements.

公开(公告)号：US10923197B2

公开(公告)日：2021-02-16

申请号：US16922037

申请日：2020-07-07

Applicant: SanDisk Technologies LLC

Inventor： Ching-Huang Lu ,  Ashish Baraskar ,  Vinh Diep

IPC: G11C11/34 ,  G11C16/14 ,  G11C16/04 ,  H01L27/1157 ,  G11C16/34 ,  H01L27/11578

Abstract: Techniques are provided for optimizing an erase operation in a memory device to compensate for erase speed variations due to blocking oxide thinning In an erase operation for a block, the channels of NAND strings in different sub-blocks can be charged up by different amounts. One approach adjusts the control gate voltage of a first select gate transistor in a NAND string. This adjusts the amount of holes generated in the channel due to gate-induced drain leakage. Another approach adjusts the control gate voltage of additional select gate transistors in the NAND string to adjust the conductivity of the adjacent channel regions. Another approach applies different bit line voltages to different rows of NAND strings in each sub-block.

公开(公告)号：US10854300B2

公开(公告)日：2020-12-01

申请号：US16898145

申请日：2020-06-10

Applicant: SanDisk Technologies LLC

Inventor： Ching-Huang Lu ,  Vinh Diep ,  Zhengyi Zhang

IPC: G11C16/26 ,  G11C16/34 ,  G11C16/10 ,  G11C16/04 ,  G11C16/24

Abstract: Techniques are described for programming memory cells with reduced widening of the threshold voltage distributions. Bit line voltages are adjusted during verify tests for memory cells assigned to the upper data state in a pair of adjacent data states which are concurrently verified. An elevated bit line voltage is applied and then stepped up in successive program loops. A lower, fixed bit line voltage is used for verifying the lower data state in the pair of adjacent data states. In one option, the step size increases progressively over the program loops. In another option, the minimum level of the elevated bit line voltage is lower for higher data states. In another option, the minimum level of the elevated bit line voltage is set as a function of data states, program-erase cycles and/or temperature.

公开(公告)号：US10762973B1

公开(公告)日：2020-09-01

申请号：US16408975

申请日：2019-05-10

Applicant: SanDisk Technologies LLC

Inventor： Ching-Huang Lu ,  Zhengyi Zhang

IPC: G11C16/34 ,  G11C16/24 ,  G11C16/16 ,  G11C16/08

Abstract: Program disturb is suppressed during a program recovery phase of a program operation in a memory device. The duration of the recovery phase can be increased when the risk of program disturb is greater due to factors such as temperature, the position of the selected word line, the number of program-erase cycles and the program pulse magnitude. In other approaches, the risk of program disturb is reduced by providing an early ramp down of the voltages of the drain-side word line relative to a ramp down of the voltages of the source-side word lines, providing an early ramp down of the bit line voltage of the inhibited NAND strings relative to the ramp down of the select gate voltage or setting a lower recovery voltage for the source-side word lines relative to the recovery voltage of the drain-side word lines.

公开(公告)号：US10741253B1

公开(公告)日：2020-08-11

申请号：US16280297

申请日：2019-02-20

Applicant: SanDisk Technologies LLC

Inventor： Ching-Huang Lu ,  Ashish Baraskar ,  Vinh Diep

IPC: G11C7/00 ,  G11C16/14 ,  G11C16/04 ,  H01L27/1157 ,  G11C16/34 ,  H01L27/11578

Abstract: Techniques are provided for optimizing an erase operation in a memory device to compensate for erase speed variations due to blocking oxide thinning In an erase operation for a block, the channels of NAND strings in different sub-blocks can be charged up by different amounts. One approach adjusts the control gate voltage of a first select gate transistor in a NAND string. This adjusts the amount of holes generated in the channel due to gate-induced drain leakage. Another approach adjusts the control gate voltage of additional select gate transistors in the NAND string to adjust the conductivity of the adjacent channel regions. Another approach applies different bit line voltages to different rows of NAND strings in each sub-block.

公开(公告)号：US20200211663A1

公开(公告)日：2020-07-02

申请号：US16233723

申请日：2018-12-27

Applicant: SanDisk Technologies LLC

Inventor： Ashish Baraskar ,  Ching-Huang Lu ,  Vinh Diep ,  Yingda Dong

IPC: G11C16/34 ,  G11C16/10 ,  G11C11/56 ,  G11C16/24 ,  G11C16/26

Abstract: Techniques are provided to reduce neighbor word line interference and charge loss in a multi-pass program operation. In one implementation, the first pass of a multi-pass program operation uses one or more program pulses without performing associated verify tests. The memory cells may be programmed to different intermediate threshold voltage (Vth) distributions in the first program pass. Different bit line voltages can be used to obtain the different intermediate Vth distributions when the single program pulse is applied. In other cases, multiple program pulses are applied without performing verify tests. The intermediate Vth distributions can be provided for the memory cells assigned to the higher data states but not the lower data states, or for memory cells assigned to both the higher and lower data states.

公开(公告)号：US20190311772A1

公开(公告)日：2019-10-10

申请号：US15948761

申请日：2018-04-09

Applicant: SanDisk Technologies LLC

Inventor： Vinh Diep ,  Ching-Huang Lu ,  Zhengyi Zhang ,  Yingda Dong

IPC: G11C16/34 ,  G11C16/04 ,  G11C16/10 ,  G11C16/14

Abstract: Apparatuses and techniques are described for programming memory cells with a narrow threshold voltage (Vth) distribution in a memory device. In one approach, the final pass of a multi-pass program operation on a word line WLn includes applying a variable voltage to WLn+1 during verify tests on WLn. The variable voltage (Vread) can be an increasing function of the verify voltage on WLn, and thus a function of the data state for which the verify test is performed. In one approach, Vread on WLn+1 is stepped up with each increase in the verify voltage on WLn. The step size in Vread can be the same as, or different than, the step size in the verify voltage. Vread can be different for each different verify voltage, or multiple verify voltages can be grouped for use with a common Vread.

公开(公告)号：US20190252029A1

公开(公告)日：2019-08-15

申请号：US15897550

申请日：2018-02-15

Applicant: SanDisk Technologies LLC

Inventor： Chun-Hung Lai ,  Rajdeep Gautam ,  Ching-Huang Lu ,  Shih-Chung Lee

IPC: G11C16/34 ,  G11C16/16 ,  G11C7/14 ,  G11C11/56 ,  G11C16/04

CPC classification number: G11C16/3445 ,  G11C7/14 ,  G11C11/5635 ,  G11C16/0483 ,  G11C16/16

Abstract: Apparatuses and techniques are described for reducing charge loss in a select gate transistor in a memory device. In one aspect, a dummy memory cell adjacent to a select gate transistor is weakly programmed during an erase operation by applying a program pulse to the dummy memory cell. The program pulse can be applied after an erase bias is applied to the memory cells and before an erase-verify test is performed, in one approach. The program pulse can be applied during the setup of the voltages for the erase-verify test. The magnitude of the program pulse can be increased in successive erase loops of an erase operation as the magnitude of a substrate voltage is also increased. The magnitude of the program pulse can also be set as an increasing function of a number of program-erase (P-E) cycles.

公开(公告)号：US10020314B1

公开(公告)日：2018-07-10

申请号：US15448409

申请日：2017-03-02

Applicant: SanDisk Technologies LLC

Inventor： Ashish Baraskar ,  Liang Pang ,  Yanli Zhang ,  Ching-Huang Lu ,  Yingda Dong

IPC: H01L21/336 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11556 ,  H01L27/11582 ,  H01L21/8234 ,  H01L27/11526 ,  H01L27/11573

CPC classification number: H01L27/11519 ,  H01L21/823412 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582

Abstract: Disclosed herein are methods of forming non-volatile storage. An opening may be etched through a stack of two alternating materials to a semiconductor substrate. A silicon nitride film may be formed on a vertical sidewall of the opening. The semiconductor substrate may be cleaned to remove oxide from the semiconductor substrate. The silicon nitride film protects the materials in the stack while cleaning the semiconductor substrate. The silicon nitride film may be converted to an oxide after cleaning the semiconductor substrate. A semiconductor region may be formed in contact with the cleaned semiconductor substrate. A memory cell film may be formed over the oxide in the opening. Control gates may be formed by replacing one of the materials in the stack with a conductive material. The oxide may serve as a blocking layer between the control gates and charge storage regions in the memory cell film.

公开(公告)号：US20180175054A1

公开(公告)日：2018-06-21

申请号：US15891574

申请日：2018-02-08

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Ashish Baraskar ,  Raghuveer S. Makala ,  Ching-Huang Lu ,  Yao-Sheng Lee ,  Jian Chen

IPC: H01L27/11582 ,  H01L21/28 ,  H01L27/11565 ,  H01L23/532 ,  H01L21/02 ,  H01L21/768 ,  H01L23/528

CPC classification number: H01L27/11582 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/768 ,  H01L23/528 ,  H01L23/53257 ,  H01L27/11565 ,  H01L29/40117 ,  H01L29/7926

Abstract: A three-dimensional non-volatile memory comprises a plurality of word line layers arranged alternatingly with a plurality of dielectric layers in a stack over a substrate. Higher word lines are implemented to be thicker than lower word lines in order to reduce variation in resistance among word lines.