公开(公告)号：US09953717B2

公开(公告)日：2018-04-24

申请号：US15292548

申请日：2016-10-13

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Jagdish Sabde ,  Jayavel Pachamuthu ,  Peter Rabkin

IPC: G11C16/34 ,  G11C16/04 ,  G11C16/10 ,  G11C16/14 ,  G11C16/08 ,  G11C11/56 ,  G11C16/16

CPC classification number: G11C16/3427 ,  G11C11/5628 ,  G11C11/5635 ,  G11C16/0466 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/14 ,  G11C16/16

Abstract: Systems and methods for improving performance of a non-volatile memory by utilizing one or more tier select gate transistors between different portions of a NAND string are described. A first memory string tier may comprise a first set of memory cell transistors that may be programmed to store a first set of data and a second memory string tier may comprise a second set of memory cell transistors that are arranged above the first set of transistors and that may be programmed to store a second set of data. Between the first set of memory cell transistors and the second set of memory cell transistors may comprise a tier select gate transistor in series with the first set of memory cell transistors and the second set of memory cell transistors. The tier select gate transistor may comprise a programmable transistor or a non-programmable transistor.

公开(公告)号：US09934872B2

公开(公告)日：2018-04-03

申请号：US14528711

申请日：2014-10-30

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Sagar Magia ,  Jagdish Sabde ,  Jayavel Pachamuthu

IPC: G11C29/00 ,  G11C29/52 ,  G06F3/06 ,  G11C16/34 ,  G11C29/06 ,  G11C29/42 ,  G11C29/50 ,  G11C29/04

CPC classification number: G11C29/52 ,  G06F3/0619 ,  G06F3/0652 ,  G06F3/0679 ,  G11C16/349 ,  G11C29/06 ,  G11C29/42 ,  G11C29/50004 ,  G11C2029/0409

Abstract: Techniques are presented for using erase stress and variations in the loop count (number of cycles) for various fail modes in non-volatile memories, including erase disturb and shallow erase. For detection of shallow erase, cells are programmed and then erased, where the variation (delta) in the number of erase loop counts can be used to determine defective blocks. To determine blocks prone to erase disturb, an erase stress is applied to unselected blocks, after which they are programmed: after then erasing one block, the next block can then be read to determine whether it has suffered erase disturb.

公开(公告)号：US09881929B1

公开(公告)日：2018-01-30

申请号：US15335850

申请日：2016-10-27

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Pradhyumna Ravikirthi ,  Jayavel Pachamuthu ,  Jagdish Sabde ,  Peter Rabkin

IPC: H01L27/11 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11556 ,  H01L27/11582

CPC classification number: H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582

Abstract: A first tier structure including a first alternating stack of first insulating layers and first sacrificial material layers is formed over a substrate. First support openings and first memory openings, filled with first support pillar structures and sacrificial pillar structures, respectively, are formed through the first tier structure. A second tier structure including a second alternating stack of second insulating layers and second sacrificial material layers is formed thereabove. Second support openings and second memory openings are formed through the second tier structure such that the second support openings do not overlap with the first support pillar structures and the second memory openings overlie the sacrificial pillar structures. Inter-tier memory openings are formed by removal of the sacrificial pillar structures. Memory stack structures and second support pillar structures are formed in the inter-tier memory openings and the second support openings, respectively.

公开(公告)号：US20170287566A1

公开(公告)日：2017-10-05

申请号：US15292548

申请日：2016-10-13

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Jagdish Sabde ,  Jayavel Pachamuthu ,  Peter Rabkin

IPC: G11C16/34 ,  G11C16/08 ,  G11C16/14 ,  G11C16/04 ,  G11C16/10

CPC classification number: G11C16/3427 ,  G11C11/5628 ,  G11C11/5635 ,  G11C16/0466 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/14 ,  G11C16/16

Abstract: Systems and methods for improving performance of a non-volatile memory by utilizing one or more tier select gate transistors between different portions of a NAND string are described. A first memory string tier may comprise a first set of memory cell transistors that may be programmed to store a first set of data and a second memory string tier may comprise a second set of memory cell transistors that are arranged above the first set of transistors and that may be programmed to store a second set of data. Between the first set of memory cell transistors and the second set of memory cell transistors may comprise a tier select gate transistor in series with the first set of memory cell transistors and the second set of memory cell transistors. The tier select gate transistor may comprise a programmable transistor or a non-programmable transistor.

公开(公告)号：US09653175B2

公开(公告)日：2017-05-16

申请号：US15283645

申请日：2016-10-03

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Jagdish Sabde ,  Sagar Magia ,  Khanh Nguyen

IPC: G11C16/34 ,  G11C29/02 ,  G11C29/06 ,  H01L27/1157 ,  H01L27/11582 ,  G11C16/04 ,  G11C16/16 ,  G11C29/12

CPC classification number: G11C16/3422 ,  G11C16/0466 ,  G11C16/0483 ,  G11C16/16 ,  G11C29/025 ,  G11C29/06 ,  G11C2029/1202 ,  H01L27/1157 ,  H01L27/11582

Abstract: A number of techniques for determining defects in non-volatile memory arrays are presented, which are particularly applicable to 3D NAND memory, such as that of the BiCS type. Word line to word shorts within a memory block are determined by application of an AC stress mode, followed by a defect detection operation. An inter-block stress and detection operation can be used determine word line to word line leaks between different blocks. Select gate leak line leakage, both the word lines and other select lines, is consider, as are shorts from word lines and select lines to local source lines. In addition to word line and select line defects, techniques for determining shorts between bit lines and low voltage circuitry, as in the sense amplifiers, are presented.

公开(公告)号：US09460809B2

公开(公告)日：2016-10-04

申请号：US14328021

申请日：2014-07-10

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Sagar Magia ,  Jagdish Sabde

IPC: G11C29/00 ,  G11C29/02 ,  G11C16/34 ,  G11C29/44 ,  G11C29/42 ,  G06F11/27 ,  G11C29/12

CPC classification number: G11C29/022 ,  G06F11/27 ,  G11C16/3495 ,  G11C29/42 ,  G11C29/44 ,  G11C2029/1202

Abstract: A number of techniques for determining defects in non-volatile memory arrays are presented, which are particularly applicable to 3D NAND memory, such as that of the BiCS type. Word line to word shorts within a memory block are determined by application of an AC stress mode, followed by a defect detection operation. An inter-block stress and detection operation can be used determine word line to word line leaks between different blocks. Select gate leak line leakage, both the word lines and other select lines, is consider, as are shorts from word lines and select lines to local source lines. In addition to word line and select line defects, techniques for determining shorts between bit lines and low voltage circuitry, as in the sense amplifiers, are presented.

Abstract translation: 提出了用于确定非易失性存储器阵列中的缺陷的许多技术，其特别适用于诸如BiCS类型的3D NAND存储器。 通过应用AC应力模式，随后进行缺陷检测操作来确定存储器块内的字线到字短路。 可以使用块间应力和检测操作来确定不同块之间的字线到字线泄漏。 选择栅极泄漏线泄漏，字线和其他选择线都是考虑的，也是字线的短路，并选择线到本地源极线。 除了字线和选择线缺陷之外，还提供了用于确定位线和低电压电路之间的短路的技术，如在读出放大器中。