公开(公告)号：US10515897B2

公开(公告)日：2019-12-24

申请号：US15982215

申请日：2018-05-17

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Masatoshi Nishikawa ,  Akio Nishida ,  Murshed Chowdhury ,  Takahito Fujita ,  Kiyokazu Shishido ,  Hiroyuki Ogawa

IPC: H01L29/792 ,  H01L23/532 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11573 ,  H01L21/768 ,  H01L23/522 ,  H01L29/06 ,  H01L29/08

Abstract: A semiconductor structure includes a semiconductor device, an overlying silicon nitride diffusion barrier layer, and an interconnect structure extending through the silicon nitride diffusion barrier layer. The interconnect structure includes a titanium diffusion barrier structure in contact with the silicon nitride diffusion barrier layer to form a continuous hydrogen diffusion barrier structure.

公开(公告)号：US09941297B2

公开(公告)日：2018-04-10

申请号：US15607837

申请日：2017-05-30

Applicant: SanDisk Technologies LLC

Inventor： Masatoshi Nishikawa ,  Kota Funayama ,  Toru Miwa ,  Hiroyuki Ogawa

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11524 ,  H01L27/1157

CPC classification number: H01L27/11582 ,  H01L21/2253 ,  H01L21/283 ,  H01L21/76883 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/5228 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11578 ,  H01L28/20

Abstract: A vertical, columnar resistor in a semiconductor device is provided, along with techniques for fabricating such a resistor. The resistor may be provided in a peripheral area of a 3D memory device which has a two-tier or other multi-tier stack of memory cells. The structure and fabrication of the resistor can be integrated with the structure and fabrication of the stack of memory cells. The resistor may comprise doped polysilicon. In an example implementation, a polysilicon pillar extends a height of a first tier of the stack and a metal pillar above the polysilicon pillar extends a height of a second tier of the stack.

公开(公告)号：US11024635B2

公开(公告)日：2021-06-01

申请号：US16879903

申请日：2020-05-21

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Zhixin Cui ,  Masatoshi Nishikawa ,  Yanli Zhang

IPC: H01L27/11524 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11529 ,  H01L27/11575 ,  H01L27/11578 ,  H01L21/28 ,  H01L27/11519

Abstract: A three-dimensional memory device includes alternating stacks of electrically conductive strips and spacer strips located over a substrate and laterally spaced apart among one another by memory stack assemblies. The spacer strips may include air gap strips or insulating strips. Each of the memory stack assemblies includes two two-dimensional arrays of lateral protrusion regions. Each of the lateral protrusion regions comprises a respective curved charge storage element. The charge storage elements may be discrete elements located within a respective lateral protrusion region, or may be a portion of a charge storage material layer that extends vertically over multiple electrically conductive strips. Each of the memory stack assemblies may include two rows of vertical semiconductor channels that laterally overlie a respective vertical stack of charge storage elements.

公开(公告)号：US11024385B2

公开(公告)日：2021-06-01

申请号：US16415377

申请日：2019-05-17

Applicant: SanDisk Technologies LLC

Inventor： Hardwell Chibvongodze ,  Masatoshi Nishikawa

IPC: G11C11/34 ,  G11C16/10 ,  G11C7/06 ,  G11C16/08 ,  G11C16/24 ,  G11C16/26 ,  H01L27/11524 ,  H01L27/11582 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11519 ,  H01L27/11565 ,  G11C16/34

Abstract: A semiconductor device is disclosed including an integrated memory module. The integrated memory module includes a first semiconductor die comprising first non-volatile memory cells, a second semiconductor die comprising second non-volatile memory cells, and a third semiconductor die comprising control circuitry. The first, the second and the third semiconductor die are bonded together. The control circuitry is configured to control memory operations in the first memory cells in parallel with the second memory cells.

公开(公告)号：US20200286915A1

公开(公告)日：2020-09-10

申请号：US16878865

申请日：2020-05-20

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Zhixin Cui ,  Masatoshi Nishikawa ,  Yanli Zhang

IPC: H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11578 ,  H01L21/28 ,  H01L27/11519 ,  H01L27/11575 ,  H01L27/11529 ,  H01L27/1157 ,  H01L21/764 ,  H01L29/06

Abstract: A three-dimensional memory device includes alternating stacks of electrically conductive strips and spacer strips located over a substrate and laterally spaced apart among one another by memory stack assemblies. The spacer strips may include air gap strips or insulating strips. Each of the memory stack assemblies includes two two-dimensional arrays of lateral protrusion regions. Each of the lateral protrusion regions comprises a respective curved charge storage element. The charge storage elements may be discrete elements located within a respective lateral protrusion region, or may be a portion of a charge storage material layer that extends vertically over multiple electrically conductive strips. Each of the memory stack assemblies may include two rows of vertical semiconductor channels that laterally overlie a respective vertical stack of charge storage elements.

公开(公告)号：US20200185397A1

公开(公告)日：2020-06-11

申请号：US16213180

申请日：2018-12-07

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Hardwell Chibvongodze ,  Masatoshi Nishikawa ,  Naoki Ookuma ,  Takuya Ariki ,  Toru Miwa

IPC: H01L27/11548 ,  H01L27/11526 ,  H01L27/11573 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11575 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11519 ,  H01L27/11565 ,  H01L29/423 ,  G11C16/04 ,  G11C16/26 ,  G11C16/30 ,  G11C16/24

Abstract: A three-dimensional memory device includes memory stack structures in multiple memory arrays. Bit lines are split into multiple portions traversing different memory arrays. Each sense amplifier is connected to a first portion of a respective bit line via a respective first switching transistor device, and is connected to a second portion of the respective bit line via a respective second switching transistor device. The switching transistor devices connect each sense amplifier to one portion of the bit lines without connecting to another portion of the bit lines, thereby reducing the RC delay. The switching transistor devices may be provided as vertical field effect transistors located at a memory array level, or may be provided in another semiconductor chip.

公开(公告)号：US10516025B1

公开(公告)日：2019-12-24

申请号：US16009661

申请日：2018-06-15

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Masatoshi Nishikawa ,  Hisakazu Otoi ,  Akio Nishida

IPC: H01L29/00 ,  H01L29/423 ,  H01L29/66 ,  H01L27/11556

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, and a memory stack structure extending through the alternating stack. The memory stack structure includes a tunneling dielectric layer, a vertical semiconductor channel, and a vertical stack of charge storage structures. Each of the charge storage structures includes an annular silicon nitride portion, a lower silicon nitride portion underlying the upper silicon nitride portion, and a spacer located between the upper silicon nitride portion and the lower silicon nitride portion. The upper and lower silicon nitride portions may be charge storage regions, while the spacer may be a floating gate or a dielectric spacer.

公开(公告)号：US10381376B1

公开(公告)日：2019-08-13

申请号：US16002294

申请日：2018-06-07

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Masatoshi Nishikawa ,  Xiaolong Hu ,  Yanli Zhang

IPC: H01L29/792 ,  H01L27/11582 ,  H01L29/10 ,  H01L21/8234 ,  H01L27/1157

Abstract: A three-dimensional memory device includes alternating stacks of insulating strips and electrically conductive strips located over a substrate and laterally spaced apart among one another by vertically undulating trenches. The vertically undulating trenches have a greater lateral extent at levels of the electrically conductive strips than at levels of the insulating strips. An interlaced two-dimensional array of memory stack assemblies and dielectric pillar structures are located in the vertically undulating trenches. Each memory stack assembly includes a vertical semiconductor channel and a pair of memory films including a respective pair of convex outer sidewalls that contact, or are spaced by a uniform distance from, concave sidewalls of the electrically conductive strips. Local electrical field at laterally protruding tips of the vertical semiconductor channels are enhanced due to the geometric effect provided by the concave sidewalls of the electrically conductive strips to facilitate faster program and erase operations.

公开(公告)号：US09935124B2

公开(公告)日：2018-04-03

申请号：US15219719

申请日：2016-07-26

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Masatoshi Nishikawa ,  Masafumi Miyamoto ,  Hiroyuki Ogawa

IPC: H01L27/115 ,  H01L27/11582 ,  H01L23/528 ,  H01L27/11556 ,  H01L29/06 ,  H01L21/28 ,  H01L21/311 ,  H01L23/522 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/08 ,  H01L27/1157

CPC classification number: H01L27/11582 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/31111 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/0649 ,  H01L29/0847

Abstract: Split memory cells can be provided within an alternating stack of insulating layers and word lines. At least one lower-select-gate-level electrically conductive layers and/or at least one upper-select-level electrically conductive layers without a split memory cell configuration can be provided by limiting the levels of separator insulator structures within the levels of the word lines. At least one etch stop layer can be formed above at least one lower-select-gate-level spacer material layer. An alternating stack of insulating layers and spacer material layers is formed over the at least one etch stop layer. Separator insulator structures are formed through the alternating stack employing the etch stop layer as a stopping structure. Upper-select-level spacer material layers can be subsequently formed. The spacer material layers and the select level material layers are formed as, or replaced with, electrically conductive layers.

公开(公告)号：US09935123B2

公开(公告)日：2018-04-03

申请号：US15219652

申请日：2016-07-26

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Masatoshi Nishikawa ,  Masafumi Miyamoto ,  James Kai

IPC: H01L27/115 ,  H01L27/11582 ,  H01L23/528 ,  H01L27/11556 ,  H01L29/06 ,  H01L21/28 ,  H01L21/311 ,  H01L23/522 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/08 ,  H01L27/1157

CPC classification number: H01L27/11582 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/31111 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/0649 ,  H01L29/0847

Abstract: An alternating stack of sacrificial material layers and insulating layers is formed over a substrate. Replacement of sacrificial material layers with electrically conductive layers can be performed employing a subset of openings. A predominant subset of the openings is employed to form memory stack structures therein. A minor subset of the openings is employed as access openings for introducing an etchant to remove the sacrificial material layers to form lateral recesses and to provide a reactant for depositing electrically conductive layers in the lateral recesses. By distributing the access openings across the entirety of the openings and eliminating the need to employ backside trenches for replacement of the sacrificial material layers, the size and lateral extent of backside trenches can be reduced to a level sufficient to accommodate only backside contact via structures.