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公开(公告)号：US11682442B2
公开(公告)日：2023-06-20
申请号：US17846678
申请日：2022-06-22
Applicant: SanDisk Technologies LLC
Inventor： Michael Nicolas Albert Tran , Ward Parkinson , Michael Grobis , Nathan Franklin
CPC classification number: G11C11/1659 , G11C11/1655 , G11C11/1657 , G11C11/1673 , G11C11/1675 , G11C11/1695 , G11C11/1697 , H01L27/222 , H01L43/02 , H01L43/08 , H01L27/2481
Abstract: Technology for limiting a voltage difference between two selected conductive lines in a cross-point array when using a forced current approach is disclosed. In one aspect, the selected word line voltage is clamped to a voltage limit while driving an access current through a region of the selected word line and through a region of the selected bit line. The access current flows through the memory cell to allow a sufficient voltage to successfully read or write the memory cell, while not placing undue stress on the memory cell. In some aspects, the maximum voltage that is permitted on the selected word line depends on the location of the selected memory cell in the cross-point memory array. This allows memory cells for which there is a larger IR drop to receive an adequate voltage, while not over-stressing memory cells for which there is a smaller IR drop.
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公开(公告)号：US20230005530A1
公开(公告)日：2023-01-05
申请号：US17939826
申请日：2022-09-07
Applicant: SanDisk Technologies LLC
Inventor： Nathan Franklin , Ward Parkinson , Michael Grobis , James O'Toole
Abstract: Concurrent access of multiple memory cells in a cross-point memory array is disclosed. In one aspect, a forced current approach is used in which, while a select voltage is applied to a selected bit line, an access current is driven separately through each selected word line to concurrently drive the access current separately through each selected memory cell. Hence, multiple memory cells are concurrently accessed. In some aspects, the memory cells are accessed using a self-referenced read (SRR), which improves read margin. Concurrently accessing more than one memory cell in a cross-point memory array improves bandwidth. Moreover, such concurrent accessing allows the memory system to be constructed with fewer, but larger cross-point arrays, which increases array efficiency. Moreover, concurrent access as disclosed herein is compatible with memory cells such as MRAM which require bipolar operation.
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公开(公告)号：US20220415387A1
公开(公告)日：2022-12-29
申请号：US17939818
申请日：2022-09-07
Applicant: SanDisk Technologies LLC
Inventor： Nathan Franklin , Ward Parkinson , Michael Grobis , James O'Toole
Abstract: Concurrent access of multiple memory cells in a cross-point memory array is disclosed. In one aspect, a forced current approach is used in which, while a select voltage is applied to a selected bit line, an access current is driven separately through each selected word line to concurrently drive the access current separately through each selected memory cell. Hence, multiple memory cells are concurrently accessed. In some aspects, the memory cells are accessed using a self-referenced read (SRR), which improves read margin. Concurrently accessing more than one memory cell in a cross-point memory array improves bandwidth. Moreover, such concurrent accessing allows the memory system to be constructed with fewer, but larger cross-point arrays, which increases array efficiency. Moreover, concurrent access as disclosed herein is compatible with memory cells such as MRAM which require bipolar operation.
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公开(公告)号：US11501831B2
公开(公告)日：2022-11-15
申请号：US17090438
申请日：2020-11-05
Applicant: SanDisk Technologies LLC
Inventor： Neil Robertson , Michael Grobis , Ward Parkinson
Abstract: In a memory array with a cross-point structure, at each cross-point junction a programmable resistive memory element, such as an MRAM memory cell, is connected in series with a threshold switching selector, such as an ovonic threshold switch. The threshold switching selector switches to a conducting state when a voltage above a threshold voltage is applied. When powered down for extended periods, the threshold voltage can drift upward. If the drift is excessive, this can make the memory cell difficult to access and can disturb stored data values when accessed. Techniques are presented to determine whether excessive voltage threshold drift may have occurred, including a read based test and a time based test.
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公开(公告)号：US20220335999A1
公开(公告)日：2022-10-20
申请号：US17846684
申请日：2022-06-22
Applicant: SanDisk Technologies LLC
Inventor： Michael Nicolas Albert Tran , Ward Parkinson , Michael Grobis , Nathan Franklin
Abstract: Technology for limiting a voltage difference between two selected conductive lines in a cross-point array when using a forced current approach is disclosed. In one aspect, the selected word line voltage is clamped to a voltage limit while driving an access current through a region of the selected word line and through a region of the selected bit line. The access current flows through the memory cell to allow a sufficient voltage to successfully read or write the memory cell, while not placing undue stress on the memory cell. In some aspects, the maximum voltage that is permitted on the selected word line depends on the location of the selected memory cell in the cross-point memory array. This allows memory cells for which there is a larger IR drop to receive an adequate voltage, while not over-stressing memory cells for which there is a smaller IR drop.
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Patent Agency Ranking
公开(公告)号：US12148459B2
公开(公告)日：2024-11-19
申请号：US17677666
申请日：2022-02-22
Applicant: SanDisk Technologies LLC
Inventor： Ward Parkinson , James O'Toole , Thomas Trent , Nathan Franklin , Michael Grobis , James W. Reiner , Hans Jurgen Richter , Michael Nicolas Albert Tran
Abstract: Technology for read in a cross-point memory array. Drive transistors pass read and write currents to the cross-point memory array. The read current charges a selected word line to turn on a threshold switching selector of a selected memory cell. While the threshold switching selector is on, the current (read or write) passes through the selected memory cell. The memory system applies a smaller overdrive voltage to a drive transistor when the drive transistor is passing the read current than when the drive transistor is passing the write current. A smaller overdrive voltage increases the resistance of the drive transistor. Increasing the resistance of the drive transistor increases the resistance seen by the threshold switching selector in the selected memory cell, which reduces the Ihold of the threshold switching selector.
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公开(公告)号：US11894037B2
公开(公告)日：2024-02-06
申请号：US17718759
申请日：2022-04-12
Applicant: SanDisk Technologies LLC
Inventor： Michael Grobis , James W. Reiner , Michael Nicolas Albert Tran , Juan P. Saenz , Gerrit Jan Hemink
CPC classification number: G11C11/1659 , G11C7/20 , G11C13/003 , H01L24/08 , H01L25/0657 , H01L25/18 , H01L2224/08145 , H01L2924/1431 , H01L2924/1443
Abstract: In a memory array with a cross-point structure, at each cross-point junction a programmable resistive memory element, such as an MRAM memory cell, is connected in series with a threshold switching selector, such as an ovonic threshold switch. The threshold switching selector switches to a conducting state when a voltage above a threshold voltage is applied. When powered down for extended periods, the threshold voltage can drift upward. If the drift is excessive, this can make the memory cell difficult to access and can disturb stored data values when accessed. Techniques are presented to determine whether excessive voltage threshold drift may have occurred, including a read based test and a time based test. Techniques are also presented for initializing a cross-point array, for both first fire and cold start, by using voltage levels shifted from half-select voltage levels used in a standard memory access.
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公开(公告)号：US20230100600A1
公开(公告)日：2023-03-30
申请号：US17485129
申请日：2021-09-24
Applicant: SanDisk Technologies LLC
Inventor： Michael Nicolas Albert Tran , Ward Parkinson , Michael Grobis , Nathan Franklin , Raj Ramanujan
Abstract: Technology for reading reversible resistivity cells in a memory array when using a current-force read is disclosed. The memory cells are first read using a current-force referenced read. If the current-force referenced read is successful, then results of the current-force referenced read are returned. If the current-force referenced read is unsuccessful, then a current-force self-referenced read (SRR) is performed and results of the current-force SRR are returned. The current-force referenced read provides a very fast read of the memory cells and can be successful in most cases. The current-force SRR provides a more accurate read in the event that the current-force referenced read is not successful. Moreover, the current-force referenced read may use less power than the current-force SRR. In an aspect this mixed current-force read is used for MRAM cells, which are especially challenging to read.
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公开(公告)号：US20220335998A1
公开(公告)日：2022-10-20
申请号：US17846678
申请日：2022-06-22
Applicant: SanDisk Technologies LLC
Inventor： Michael Nicolas Albert Tran , Ward Parkinson , Michael Grobis , Nathan Franklin
Abstract: Technology for limiting a voltage difference between two selected conductive lines in a cross-point array when using a forced current approach is disclosed. In one aspect, the selected word line voltage is clamped to a voltage limit while driving an access current through a region of the selected word line and through a region of the selected bit line. The access current flows through the memory cell to allow a sufficient voltage to successfully read or write the memory cell, while not placing undue stress on the memory cell. In some aspects, the maximum voltage that is permitted on the selected word line depends on the location of the selected memory cell in the cross-point memory array. This allows memory cells for which there is a larger IR drop to receive an adequate voltage, while not over-stressing memory cells for which there is a smaller IR drop.
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公开(公告)号：US20220157376A1
公开(公告)日：2022-05-19
申请号：US17099030
申请日：2020-11-16
Applicant: SanDisk Technologies LLC
Inventor： Nathan Franklin , Ward Parkinson , Michael Grobis , James O'Toole
Abstract: Concurrent access of multiple memory cells in a cross-point memory array is disclosed. In one aspect, a forced current approach is used in which, while a select voltage is applied to a selected bit line, an access current is driven separately through each selected word line to concurrently drive the access current separately through each selected memory cell. Hence, multiple memory cells are concurrently accessed. In some aspects, the memory cells are accessed using a self-referenced read (SRR), which improves read margin. Concurrently accessing more than one memory cell in a cross-point memory array improves bandwidth. Moreover, such concurrent accessing allows the memory system to be constructed with fewer, but larger cross-point arrays, which increases array efficiency. Moreover, concurrent access as disclosed herein is compatible with memory cells such as MRAM which require bipolar operation.
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