公开(公告)号：US20180175834A1

公开(公告)日：2018-06-21

申请号：US15639153

申请日：2017-06-30

Applicant: SanDisk Technologies LLC

Inventor： Primit Modi ,  Venkatesh Ramachandra ,  Tianyu Tang ,  Srinivas Rajendra

IPC: H03K3/017 ,  H03K5/156 ,  H03K5/151 ,  H03K7/08

CPC classification number: H03K3/017 ,  G11C7/04 ,  G11C7/1066 ,  G11C7/1093 ,  G11C7/222 ,  G11C29/023 ,  G11C29/028 ,  H03K5/151 ,  H03K5/1565 ,  H03K7/08

Abstract: A complementary signal path may include an amplifier circuit configured to receive a pair of complementary input signals and a data alignment circuit configured to output a pair of complementary output signals in response to the pair of complementary input signals. A control circuit may detect duty cycle distortion in the pair of complementary output signals and perform a duty cycle correction process to remove the distortion. To do so, the control circuit may search for target current amounts in response to the duty cycle distortion and inject a control current into the amplifier circuit at the target current amounts.

公开(公告)号：US20210304834A1

公开(公告)日：2021-09-30

申请号：US16828547

申请日：2020-03-24

Applicant: SanDisk Technologies LLC

Inventor： Tianyu Tang ,  Venkatesh Ramachandra

IPC: G11C29/02 ,  G11C16/10 ,  G11C16/26 ,  G11C16/30 ,  G11C29/12

Abstract: Technology is disclosed herein for a semiconductor die, and controlling operation of the semiconductor die. In some aspects, a semiconductor die is configured to test an I/O circuit on the semiconductor die. The semiconductor die has an input circuit that compares a voltage signal at one of a first input or a second input with a reference voltage at the other of the first input or the second input to generate an input voltage signal. The first input may be connected to an I/O contact. During a normal mode a control circuit on the die provides a reference voltage to second input. During a test mode, the control circuit internally loops back a test signal from an output circuit to the second input of the input circuit. Thus, the test signal avoids the I/O contact.

公开(公告)号：US10530347B2

公开(公告)日：2020-01-07

申请号：US16017286

申请日：2018-06-25

Applicant: SanDisk Technologies LLC

Inventor： Tianyu Tang ,  Venkatesh Ramachandra

IPC: H03K5/133 ,  G11C7/22 ,  G06F1/10 ,  H03K5/156

Abstract: A skew correction system includes delay circuits positioned in front of sampling circuitry. A skew correction controller first delays an input clock signal to create hold violations. Then with, with the delay of an input clock signal fixed at a reference delay amount, the skew correction controller delays input data signals first to remove or reduce the hold violations, and then to create setup violations. Based on the delaying, the skew correction controller identifies data valid windows for the input data signals, and in turn, identifies target delay amounts that position a delayed clock signal in target sampling positions.

公开(公告)号：US20190333551A1

公开(公告)日：2019-10-31

申请号：US15965099

申请日：2018-04-27

Applicant: SanDisk Technologies LLC

Inventor： Tianyu Tang ,  Venkatesh Ramachandra

IPC: G11C7/22 ,  H03K5/133 ,  H03K3/037 ,  H03K5/1534 ,  H03K3/017

Abstract: A duty cycle correction system corrects for duty cycle distortion by measuring average time interval durations of consecutive intervals of an input signal. The system generates complementary ramp signals that have cross-points indicating midpoints of the intervals, and detects those cross-points. An output circuit of the duty cycle correction system generates an output signal that performs rising and falling transitions in response to the detected cross-points.

公开(公告)号：US20190296723A1

公开(公告)日：2019-09-26

申请号：US16017286

申请日：2018-06-25

Applicant: SanDisk Technologies LLC

Inventor： Tianyu Tang ,  Venkatesh Ramachandra

IPC: H03K5/133 ,  G06F1/10 ,  G11C7/22

Abstract: A skew correction system includes delay circuits positioned in front of sampling circuitry. A skew correction controller first delays an input clock signal to create hold violations. Then with, with the delay of an input clock signal fixed at a reference delay amount, the skew correction controller delays input data signals first to remove or reduce the hold violations, and then to create setup violations. Based on the delaying, the skew correction controller identifies data valid windows for the input data signals, and in turn, identifies target delay amounts that position a delayed clock signal in target sampling positions.

公开(公告)号：US20190109584A1

公开(公告)日：2019-04-11

申请号：US15875400

申请日：2018-01-19

Applicant: SanDisk Technologies LLC

Inventor： Tianyu Tang ,  Venkatesh Ramachandra ,  Srinivas Rajendra

IPC: H03K3/017 ,  H03K17/687 ,  H03M1/66

Abstract: A correction system is configured to correct for duty cycle distortion and/or cross-point distortion in a pair of sample signals. A slope adjustment circuit is configured to generate a plurality of pairs of intermediate signals according to a plurality of drive strengths. A measurement circuit is configured to measure for duty cycle distortion and/or cross-point distortion, and the slope adjustment circuit is configured to set the plurality of drive strengths based on the measurement. The setting of the drive strengths may reduce certain rising and falling slopes of certain transitions of the plurality of intermediate signals, which in turn may reduce duty cycle distortion and/or cross-point distortion in the sample signals.

公开(公告)号：US09673798B1

公开(公告)日：2017-06-06

申请号：US15226574

申请日：2016-08-02

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Tianyu Tang ,  Venkatesh Ramachandra ,  Srinivas Rajendra

IPC: G11C7/22 ,  H03K5/156 ,  G11C8/18 ,  G11C13/00 ,  G11C16/32

CPC classification number: H03K5/1565 ,  G11C7/222 ,  G11C13/0021 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C16/0483 ,  G11C16/32 ,  G11C2207/2254 ,  G11C2213/71 ,  G11C2213/75 ,  G11C2213/77

Abstract: Systems and methods for generating periodic signals with reduced duty cycle variation are described. In some cases, a calibration procedure may be performed prior to a memory operation (e.g., prior to a read operation or a programming operation) in which a duty cycle correction circuit receives an input signal (e.g., an input clock signal), steps through various delay settings to determine a first delay setting corresponding with a signal high time for the input signal and a second delay setting corresponding with a signal low time for the input signal, generates a delayed version of the input signal corresponding with a mid-point delay setting between the first delay setting and the second delay setting, and generates a corrected signal using the delayed version of the input signal and the input signal.