公开(公告)号：US20200251443A1

公开(公告)日：2020-08-06

申请号：US16263058

申请日：2019-01-31

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Senaka KANAKAMEDALA ,  Raghuveer S. MAKALA ,  Yao-Sheng LEE ,  Jian CHEN

IPC: H01L23/00 ,  H01L25/18 ,  H01L23/522 ,  H01L23/538 ,  H01L21/822 ,  H01L21/033

Abstract: A first semiconductor die and a second semiconductor die can be bonded in a manner that enhances alignment of bonding pads. Non-uniform deformation of a first wafer including first semiconductor dies can be compensated for by forming a patterned stress-generating film on a backside of the first wafer. Metallic bump portions can be formed on concave surfaces of metallic bonding pads by a selective metal deposition process to reduce gaps between pairs of bonded metallic bonding pads. Pad-to-pad pitch can be adjusted on a semiconductor die to match the pad-to-pad pitch of another semiconductor die employing a tilt-shift operation in a lithographic exposure tool. A chuck configured to provide non-uniform displacement across a wafer can be employed to hold a wafer in a contoured shape for bonding with another wafer in a matching contoured position. Independently height-controlled pins can be employed to hold a wafer in a non-planar configuration.

公开(公告)号：US20180108671A1

公开(公告)日：2018-04-19

申请号：US15296380

申请日：2016-10-18

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Fabo YU ,  Jayavel PACHAMUTHU ,  Jongsun SEL ,  Tuan PHAM ,  Cheng-Chung CHU ,  Yao-Sheng LEE ,  Kensuke YAMAGUCHI ,  Masanori TERAHARA ,  Shuji MINAGAWA

IPC: H01L27/115 ,  H01L29/06 ,  H01L21/762

CPC classification number: H01L27/11575 ,  H01L21/76229 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11582 ,  H01L29/0607 ,  H01L29/0649

Abstract: Memory openings and support openings can be formed through an alternating stack of insulating layers and sacrificial material layers. A set of dielectric layers and at least one semiconductor material layer can be sequentially deposited in each of the memory openings and the support openings. The at least one semiconductor material layer is removed from inside the support openings, while the at least one semiconductor material layer is not removed from inside the memory openings. Memory stack structures and support pillar structures are formed in the memory openings and the support openings, respectively. The sacrificial material layers are replaced with electrically conductive layers. Removal of the at least one semiconductor material layer from the support pillar structures reduces or eliminates leakage current through the support pillar structures.

公开(公告)号：US20210327890A1

公开(公告)日：2021-10-21

申请号：US16849664

申请日：2020-04-15

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Raghuveer S. MAKALA ,  Senaka KANAKAMEDALA ,  Fei ZHOU ,  Yao-Sheng LEE

IPC: H01L27/11556 ,  H01L27/11582 ,  H01L23/538 ,  H01L29/423

Abstract: An alternating stack of insulating layers and spacer material layers can be formed over a substrate. The spacer material layers may be formed as, or may be subsequently replaced with, electrically conductive layers. A memory opening can be formed through the alternating stack, and annular lateral recesses are formed at levels of the insulating layers. Metal portions are formed in the annular lateral recesses, and a semiconductor material layer is deposited over the metal portions. Metal-semiconductor alloy portions are formed by performing an anneal process, and are subsequently removed by performing a selective etch process. Remaining portions of the semiconductor material layer include a vertical stack of semiconductor material portions, which may be optionally converted, partly or fully, into silicon nitride material portions. The semiconductor material portions and/or the silicon nitride material portions can be employed as discrete charge storage elements.

公开(公告)号：US20210265372A1

公开(公告)日：2021-08-26

申请号：US16801456

申请日：2020-02-26

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Senaka KANAKAMEDALA ,  Raghuveer S. MAKALA ,  Yao-Sheng LEE

IPC: H01L27/11556 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11582 ,  H01L23/532

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and word lines that are made of molybdenum layers located over a substrate, and memory stack structures extending through each layer in the alternating stack. Each of the memory stack structures includes a memory film and a vertical semiconductor channel contacting an inner sidewall of the memory film. Each memory film includes a vertical stack of discrete tubular dielectric metal oxide spacers in contact with a respective one of the molybdenum layers, a continuous silicon oxide blocking dielectric layer contacting an inner sidewall of each of the tubular dielectric metal oxide spacers, a vertical stack of charge storage material portions, and a tunneling dielectric layer contacting each of the charge storage material portions and the vertical semiconductor channel.

公开(公告)号：US20190148506A1

公开(公告)日：2019-05-16

申请号：US15813579

申请日：2017-11-15

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Senaka Krishna KANAKAMEDALA ,  Yoshihiro KANNO ,  Raghuveer S. MAKALA ,  Yanli ZHANG ,  Jin LIU ,  Murshed CHOWDHURY ,  Yao-Sheng LEE

IPC: H01L29/423 ,  H01L27/11556 ,  H01L27/11582 ,  H01L23/522 ,  H01L29/66 ,  H01L29/49

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate. Memory stack structures are located in a memory array region, each of which includes a memory film and a vertical semiconductor channel. Contact via structures located in the terrace region and contact a respective one of the electrically conductive layers. Each of the electrically conductive layers has a respective first thickness throughout the memory array region and includes a contact portion having a respective second thickness that is greater than the respective first thickness within a terrace region. The greater thickness of the contact portion prevents an etch-through during formation of contact via cavities for forming the contact via structures.

公开(公告)号：US20180151497A1

公开(公告)日：2018-05-31

申请号：US15581575

申请日：2017-04-28

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Raghuveer S. MAKALA ,  Murshed CHOWDHURY ,  Keerti SHUKLA ,  Tomohisa ABE ,  Yao-Sheng LEE ,  James KAI

IPC: H01L23/535 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11565 ,  H01L29/167 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L23/535 ,  H01L21/28518 ,  H01L21/76805 ,  H01L21/76843 ,  H01L21/76889 ,  H01L21/76895 ,  H01L23/485 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L27/0688 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582 ,  H01L29/167

Abstract: A three-dimensional memory device includes driver transistors containing boron doped semiconductor active regions, device contact via structures in physical contact with the boron doped semiconductor active regions, the device contact via structures containing at least one of tantalum, tungsten, and cobalt, and a three-dimensional memory array located over the driver transistors and including an alternating stack of insulating layers and electrically conductive layers and memory structures vertically extending through the alternating stack.