公开(公告)号：US20180174668A1

公开(公告)日：2018-06-21

申请号：US15491691

申请日：2017-04-19

Applicant: SanDisk Technologies LLC

Inventor： Anurag Nigam ,  Yukeun Sim ,  Jingwen Ouyang ,  Yingchang Chen

IPC: G11C29/00 ,  G11C11/419 ,  G11C11/418

CPC classification number: G11C29/38 ,  G11C7/1009 ,  G11C13/0026 ,  G11C13/0033 ,  G11C13/004 ,  G11C29/025 ,  G11C29/026 ,  G11C29/44 ,  G11C29/76 ,  G11C29/789 ,  G11C29/804 ,  G11C29/81 ,  G11C29/82 ,  G11C2029/1204 ,  G11C2029/1208 ,  G11C2029/4402 ,  G11C2213/71

Abstract: Techniques and memory devices are provided in which bit line short circuits are detected and groups of bit lines are masked off. A process tests groups of bit lines which are connected to a sense circuit. A masking latch is provided to store test results for each group of bit lines. Once the testing of a group is completed, the test result is communicated to a controller. Moreover, the same masking latch can store and communicate test results for multiple groups of bit lines which are connected to a sense circuit. In a user mode, a masking latch stores masking data for each group of bit lines. In response to a power on reset, the masking data is loaded into the masking latches and remains there over multiple write and read operation, until a next power on reset occurs.

公开(公告)号：US09830987B2

公开(公告)日：2017-11-28

申请号：US15151359

申请日：2016-05-10

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Chang Siau ,  Xiaowei Jiang ,  Yingchang Chen

IPC: G11C7/02 ,  G11C13/00 ,  G11C7/04 ,  G11C7/06 ,  G11C7/12 ,  G11C7/14 ,  G11C11/56 ,  G11C16/24 ,  G11C16/26

CPC classification number: G11C13/004 ,  G11C7/04 ,  G11C7/062 ,  G11C7/067 ,  G11C7/12 ,  G11C7/14 ,  G11C11/5642 ,  G11C13/0069 ,  G11C16/24 ,  G11C16/26 ,  G11C2013/0042 ,  G11C2013/0045 ,  G11C2207/063

Abstract: Methods for precharging bit lines using closed-loop feedback are described. In one embodiment, a sense amplifier may include a bit line precharge circuit for setting a bit line to a read voltage prior to sensing a memory cell connected to the bit line. The bit line precharge circuit may include a first transistor in a source-follower configuration with a first gate and a first source node electrically coupled to the bit line. By applying local feedback from the first source node to the first gate, the bit line settling time may be reduced. In some cases, a first voltage applied to the first gate may be determined based on a first current drawn from the first bit line. Thus, the first voltage applied to the first gate may vary over time depending on the conductivity of a selected memory cell connected to the bit line.

公开(公告)号：US11024392B1

公开(公告)日：2021-06-01

申请号：US16724896

申请日：2019-12-23

Applicant: SanDisk Technologies LLC

Inventor： Yingchang Chen ,  Seungpil Lee ,  Ali Al-Shamma

IPC: G11C16/26 ,  G11C16/04 ,  G11C11/56

Abstract: A sense amplifier for a memory circuit is presented that can sense a selected memory cell in either a first sensing mode, in which current from the selected memory cell flows from the memory cells into the sense amplifier, or a second sensing mode, in which current is discharged from the sense amplifier through the selected memory cell. In the first sensing mode, current from a selected memory cell is conducted through cascaded PMOS transistors to charge a sensing node, with the resultant voltage level on the sensing node used to determine the result of the sensing operation.

公开(公告)号：US20200234743A1

公开(公告)日：2020-07-23

申请号：US16251484

申请日：2019-01-18

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Yadhu Vamshi Vancha ,  Ali Al-Shamma ,  Yingchang Chen ,  Jeffrey Lee ,  Tz-Yi Liu

IPC: G11C7/06 ,  G11C11/16

Abstract: A circuit or associated system or apparatus includes a first transistor, a second transistor, a first switch, a second switch, a first current source, and a third switch. The first transistor is configured to sample a first current of a control line. The second transistor is configured to apply a second current to the control line. The second transistor is also configured to match the second current to the first current. The first switch is connected in series between a control terminal of the first transistor and a control terminal of the second transistor. The second switch is connected in series between the second transistor and the control line. The third switch is connected in series between the first current source and the control line.

公开(公告)号：US10290332B1

公开(公告)日：2019-05-14

申请号：US15799688

申请日：2017-10-31

Applicant: SanDisk Technologies LLC

Inventor： Yukeun Sim ,  Anurag Nigam ,  Yingchang Chen

IPC: G11C5/06 ,  G11C7/08 ,  G11C7/10 ,  G11C7/22

Abstract: A system may include a controller, a data receiving circuit, and a plurality of banks. The banks may send data to the data receiving circuit via a common data bus. The controller may control the communication of the data to the receiving circuit by sending control signals and clock signals to the banks. Relative lengths of control signal paths and clock signal paths may be directly related to each other and inversely related to relative lengths of data paths.

公开(公告)号：US20180294017A1

公开(公告)日：2018-10-11

申请号：US15789638

申请日：2017-10-20

Applicant: SanDisk Technologies LLC

Inventor： Yingchang Chen ,  Chun-Ju Chu

IPC: G11C7/10 ,  G11C7/08 ,  G11C7/14

CPC classification number: G11C7/1051 ,  G11C7/02 ,  G11C7/062 ,  G11C7/067 ,  G11C7/08 ,  G11C7/106 ,  G11C7/12 ,  G11C7/14 ,  G11C29/021 ,  G11C29/028

Abstract: A sense circuit includes memory cell characterization circuitry, storage circuitry, switching circuitry, and bit line biasing circuitry. The sense circuit is configured to perform a sense operation to sense a characterization of a memory cell. During a pre-charge phase, the memory cell characterization circuitry and the bit line biasing circuitry set differential voltages in the storage circuitry to levels dependent on input offset voltages according to certain polarities. The storage circuitry maintains the differential voltages during the sense phase, allowing the memory cell characterization circuitry to cancel output the input offset voltages when generating output voltages used to identify a characterization of the memory cell. The memory cell characterization circuitry also generates its output voltage based on a reference current through a reference bit line. Doing so may allow the memory cell characterization circuitry to cancel out background noise current generated on the bit line during the sense operation.

公开(公告)号：US20170199668A1

公开(公告)日：2017-07-13

申请号：US15402180

申请日：2017-01-09

Applicant: SanDisk Technologies LLC

Inventor： Jingwen Ouyang ,  Tz-Yi Liu ,  Henry Zhang ,  Yingchang Chen

IPC: G06F3/06

CPC classification number: G06F3/061 ,  G06F3/0655 ,  G06F3/0679 ,  G06F3/0688

Abstract: Apparatuses, systems, and methods are disclosed for controlling a data path for non-volatile memory. An apparatus includes one or more memory die. A memory die includes a memory core. A memory core includes an array of non-volatile memory cells and an internal data pipeline. A memory die includes a buffer that stores data associated with storage operations for a memory core. A memory die includes an internal controller that communicates with a memory core to initiate storage operations. An internal controller may delay initiating a storage operation in response to determining that an internal data pipeline and a buffer are both full.

公开(公告)号：US09704572B2

公开(公告)日：2017-07-11

申请号：US14663775

申请日：2015-03-20

Applicant: SanDisk Technologies LLC

Inventor： Yingchang Chen ,  Anurag Nigam ,  Chang Siau

IPC: G11C13/00 ,  G11C11/16 ,  G11C16/26 ,  G11C27/02

CPC classification number: G11C13/004 ,  G11C11/1673 ,  G11C11/1675 ,  G11C13/0069 ,  G11C16/26 ,  G11C27/024 ,  G11C2013/0045 ,  G11C2013/0054 ,  G11C2013/0088 ,  G11C2213/71

Abstract: A non-volatile memory is described that includes a sense amplifier that maintains a bit line voltage and output of the sense amplifier at a substantially constant voltage during read operations. During a preset phase, an output of the sense amplifier that is coupled to a selected bit line is grounded. At least one capacitor is precharged during the preset phase. During a sense phase, the sense amplifier output is disconnected from ground while the memory array is biased for reading a selected memory cell. A resulting cell current is integrated by the at least one capacitor. The integrated cell current discharges a sense node from the precharge level to an accurate voltage level based on the resulting cell current.