公开(公告)号：US20220077705A1

公开(公告)日：2022-03-10

申请号：US17417482

申请日：2019-12-18

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Kei TAKAHASHI ,  Takayuki IKEDA ,  Munehiro KOZUMA ,  Takanori MATSUZAKI ,  Takahiko ISHIZU ,  Takeshi AOKI

IPC: H02J7/00

Abstract: A secondary battery deteriorates due to repeated charging and discharging, which leads to a decrease in a battery voltage and a battery capacity. The lifetime of a secondary battery is prolonged by preventing charging at an excessive charging value that would be caused by deterioration of the secondary battery. By performing charge control in consideration of the degree of deterioration of a secondary battery, a longer lifetime of a secondary battery can be achieved. In charging a secondary battery, a charge control circuit controls a current value to a preset value, and a charging current control circuit (specifically a circuit including an error amplifier) included in a protection circuit determines a current value supplied to the secondary battery. That is, the current value supplied to the secondary battery is controlled by both the charge control circuit and the charging current control circuit that is a part of the protection circuit.

公开(公告)号：US20220020793A1

公开(公告)日：2022-01-20

申请号：US17490009

申请日：2021-09-30

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yoshiyuki KUROKAWA ,  Takayuki IKEDA ,  Hikaru TAMURA ,  Munehiro KOZUMA ,  Masataka IKEDA ,  Takeshi AOKI

IPC: H01L27/146 ,  H01L29/786 ,  H01L31/105 ,  H04N5/361 ,  H04N5/374 ,  H04N5/378

Abstract: In a CMOS image sensor in which a plurality of pixels is arranged in a matrix, a transistor in which a channel formation region includes an oxide semiconductor is used for each of a charge accumulation control transistor and a reset transistor which are in a pixel portion. After a reset operation of the signal charge accumulation portion is performed in all the pixels arranged in the matrix, a charge accumulation operation by the photodiode is performed in all the pixels, and a read operation of a signal from the pixel is performed per row. Accordingly, an image can be taken without a distortion.

公开(公告)号：US20210408902A1

公开(公告)日：2021-12-30

申请号：US17288957

申请日：2019-10-21

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Kei TAKAHASHI ,  Takeshi AOKI

IPC: H02M3/155 ,  H02M1/00 ,  H01L27/108 ,  H01L27/12 ,  H01L29/786

Abstract: A power supply circuit with a novel structure is provided. The power supply circuit includes a power converter circuit supplying power to a load; a current sensing circuit generating a first signal including data on a current flowing through the load; a voltage sensing circuit generating a second signal including data on a voltage applied to the load; a correction circuit that includes a digital filter, a digital-analog converter circuit to which a signal output from the digital filter is input, and a sample-and-hold circuit for retaining a signal output from the digital-analog converter circuit and generates a third signal obtained by correcting the second signal; a selection circuit selecting the first signal or the third signal; an output circuit generating an output signal for controlling the power converter circuit in accordance with the signal selected by the selection circuit; and a control signal generation circuit controlling switching between a first operation for generating the output signal in accordance with the first signal and generating the third signal and a second operation for generating the output signal in accordance with the third signal.

公开(公告)号：US20180109752A1

公开(公告)日：2018-04-19

申请号：US15729169

申请日：2017-10-10

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Takeshi AOKI ,  Munehiro KOZUMA ,  Yoshiyuki KUROKAWA

IPC: H04N5/455 ,  H03M99/00

CPC classification number: H04N5/455 ,  G11C14/0072 ,  H03M99/00 ,  H04H40/00 ,  H04N21/442

Abstract: A decoder with reduced power consumption is provided. The decoder includes a first circuit and a second circuit for holding data. The second circuit includes a first transistor, a second transistor, and a third transistor. The first transistor and the second transistor include an oxide semiconductor in a channel formation region. The third transistor includes silicon in a channel formation region. A gate of the second transistor is electrically connected to one of a source and a drain of the first transistor and a gate of the third transistor is electrically connected to one of a source and a drain of the second transistor. The decoder is configured to provide or stop power supply to the semiconductor device depending on a packet ID of a header portion of the data and to perform data storing or restoring of data between the first circuit and the second circuit.

公开(公告)号：US20180101359A1

公开(公告)日：2018-04-12

申请号：US15729150

申请日：2017-10-10

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shintaro HARADA ,  Yoshiyuki KUROKAWA ,  Takeshi AOKI

IPC: G06F7/544 ,  G06N3/063 ,  G06N3/04 ,  H01L29/786

CPC classification number: G06F7/5443 ,  G06N3/04 ,  G06N3/0635 ,  H01L29/7869

Abstract: A semiconductor device capable of performing product-sum operation is provided. The semiconductor device includes a first memory cell, a second memory cell, and an offset circuit. The semiconductor device retains first analog data and reference analog data in the first memory cell and the second memory cell, respectively. A potential corresponding to second analog data is applied to each of them as a selection signal, whereby current depending on the sum of products of the first analog data and the second analog data is obtained. The offset circuit includes a constant current circuit comprising a transistor and a capacitor. A first terminal of the transistor is electrically connected to a first gate of the transistor and a first terminal of the capacitor. A second gate of the transistor is electrically connected to a second terminal of the capacitor. A voltage between the first terminal and the second gate of the transistor is held in the capacitor, whereby a change in source-drain current of the transistor can be suppressed.

公开(公告)号：US20150341035A1

公开(公告)日：2015-11-26

申请号：US14725308

申请日：2015-05-29

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Munehiro KOZUMA ,  Yoshiyuki KUROKAWA ,  Takayuki IKEDA ,  Takeshi AOKI

IPC: H03K19/0944 ,  H01L29/24 ,  H01L27/12 ,  H03K19/177 ,  H01L29/786

CPC classification number: H03K19/0013 ,  H01L27/1225 ,  H01L27/124 ,  H01L29/24 ,  H01L29/7869 ,  H03K19/09441 ,  H03K19/1737 ,  H03K19/17728 ,  H03K19/17748 ,  H03K19/1776

Abstract: A programmable logic device includes a plurality of programmable logic elements (PLE) whose electrical connection is controlled by first configuration data. Each of The PLEs includes an LUT in which a relationship between a logic level of an input signal and a logic level of an output signal is determined by second configuration data, an FF to which the output signal of the LUT is input, and an MUX. The MUX includes at least two switches each including first and second transistor. A signal including third configuration data is input to a gate of the second transistor through the first transistor. The output signal of the LUT or an output signal of the FF is input to one of a source and a drain of the second transistor.

Abstract translation: 可编程逻辑器件包括多个可编程逻辑元件（PLE），其电连接由第一配置数据控制。 每个PLE包括LUT，其中输入信号的逻辑电平和输出信号的逻辑电平之间的关系由第二配置数据确定，输入LUT的输出信号的FF和MUX 。 MUX包括至少两个开关，每个开关包括第一和第二晶体管。 包括第三配置数据的信号通过第一晶体管输入到第二晶体管的栅极。 LUT的输出信号或FF的输出信号被输入到第二晶体管的源极和漏极之一。

公开(公告)号：US20150311897A1

公开(公告)日：2015-10-29

申请号：US14689262

申请日：2015-04-17

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Nora BJORKLUND ,  Takeshi AOKI ,  Yoshiyuki KUROKAWA

IPC: H03K19/177 ,  H03K19/173

CPC classification number: H03K19/1776 ,  H03K19/1733 ,  H03K19/17736

Abstract: A dynamic reconfigurable semiconductor device is provided. The semiconductor device includes two logic blocks, a pass transistor, two selection transistors and a precharge transistor. The two selection transistors are arranged to sandwich the pass transistor so that a source and a drain of the pass transistor are located between the sources of the two selection transistors. The sources and the drains of the two selection transistors are located between the two logic blocks. When the two selection transistors are in off-state, a potential can be supplied to the source or the drain of the pass transistor via the precharge transistor, and by electrical conduction, another potential for a context is applied to the gate of the pass transistor. When the context is executed, the gate of the pass transistor is in a floating state, the two selection transistors are in on-state, and the precharge transistor is in off-state.

Abstract translation: 提供动态可重构半导体器件。 半导体器件包括两个逻辑块，传输晶体管，两个选择晶体管和预充电晶体管。 两个选择晶体管被布置成夹持传输晶体管，使得传输晶体管的源极和漏极位于两个选择晶体管的源极之间。 两个选择晶体管的源极和漏极位于两个逻辑块之间。 当两个选择晶体管处于截止状态时，可以通过预充电晶体管将电位提供给传输晶体管的源极或漏极，并且通过电导通，将上下文的另一个电位施加到传输晶体管的栅极 。 当执行上下文时，传输晶体管的栅极处于浮置状态，两个选择晶体管处于导通状态，并且预充电晶体管处于截止状态。

公开(公告)号：US20150249800A1

公开(公告)日：2015-09-03

申请号：US14712270

申请日：2015-05-14

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Takeshi AOKI ,  Hikaru TAMURA

IPC: H04N5/374 ,  H01L27/146

CPC classification number: H04N5/3741 ,  G01J1/44 ,  H01L27/14612 ,  H01L27/14643 ,  H01L31/02019

Abstract: This invention has for purpose to provide a photosensor that is small in size and can obtain high-contrast image data and to provide a semiconductor device including the photosensor. In the photosensor including a light-receiving element, a transistor serving as a switching element, and a charge retention node electrically connected to the light-receiving element through the transistor, the reduction in charge held in the charge retention node is suppressed by extending the fall time of the input waveform of a driving pulse supplied to the transistor to turn off the transistor.

Abstract translation: 本发明的目的是提供一种尺寸小且可以获得高对比度图像数据并提供包括光电传感器的半导体器件的光电传感器。 在包含光接收元件，用作开关元件的晶体管和通过晶体管电连接到光接收元件的电荷保持节点的光电传感器中，通过延长电荷保持节点的电荷的减少， 提供给晶体管的驱动脉冲的输入波形的下降时间关闭晶体管。

公开(公告)号：US20130299888A1

公开(公告)日：2013-11-14

申请号：US13942428

申请日：2013-07-15

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yoshiyuki KUROKAWA ,  Takayuki IKEDA ,  Hikaru TAMURA ,  Munehiro KOZUMA ,  Masataka IKEDA ,  Takeshi AOKI

IPC: H01L27/146

CPC classification number: H01L27/14616 ,  H01L27/14603 ,  H01L27/14632 ,  H01L27/14636 ,  H01L27/14643 ,  H01L29/7869 ,  H01L31/1055 ,  H04N5/361 ,  H04N5/374 ,  H04N5/378

Abstract: In a CMOS image sensor in which a plurality of pixels is arranged in a matrix, a transistor in which a channel formation region includes an oxide semiconductor is used for each of a charge accumulation control transistor and a reset transistor which are in a pixel portion. After a reset operation of the signal charge accumulation portion is performed in all the pixels arranged in the matrix, a charge accumulation operation by the photodiode is performed in all the pixels, and a read operation of a signal from the pixel is performed per row. Accordingly, an image can be taken without a distortion.

公开(公告)号：US20130222584A1

公开(公告)日：2013-08-29

申请号：US13772663

申请日：2013-02-21

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Takeshi AOKI ,  Takayuki IKEDA ,  Yurika SATO ,  Koji DAIRIKI

IPC: H04N5/335 ,  H04N7/18 ,  H04N5/378 ,  H04N5/232

CPC classification number: H04N5/335 ,  H04N5/23254 ,  H04N5/378 ,  H04N7/18

Abstract: Provided is an image sensor having a pixel includes a photoelectric conversion element; a capacitor which is connected between the photoelectric conversion element; a reset circuit which resets a potential of a node between the photoelectric conversion element and the capacitor; an amplifier circuit which outputs a signal corresponding to the potential of the node; and a switch which controls electrical conduction between the amplifier circuit and a vertical signal line. When the node is brought into an electrically floating state, the potential of the optical signal is stored in the node in a state of being inverted. When an optical signal is detected while the potential is stored in the node, the potential of the node increases in accordance with an output potential of the photoelectric conversion element, and thus the potential of the node corresponds to a difference in potential between the optical signals in different light-receiving periods.

Abstract translation: 提供一种具有像素的图像传感器，包括光电转换元件; 连接在光电转换元件之间的电容器; 复位电路，其复位所述光电转换元件与所述电容器之间的节点的电位; 输出对应于该节点的电位的信号的放大器电路; 以及控制放大器电路和垂直信号线之间的导通的开关。 当节点处于电浮动状态时，光信号的电位以倒置的状态存储在节点中。 当在电位存储在节点中时检测到光信号时，节点的电位根据光电转换元件的输出电位而增加，因此节点的电位对应于光信号之间的电位差 在不同的光接收期。