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公开(公告)号：US09807303B2
公开(公告)日：2017-10-31
申请号：US15163373
申请日：2016-05-24
Applicant: Sony Corporation
Inventor： Minoru Ishida
CPC classification number: H04N5/23238 , G06T5/006 , G06T2207/20221 , H04N5/2252 , H04N5/2258 , H04N5/23219 , H04N5/23222 , H04N5/23235 , H04N5/23293
Abstract: An information processing apparatus includes a first optical system, a second optical system, and a casing. The first optical system is configured to input light into a first imaging device. The second optical system is configured to input light into a second imaging device. The casing includes one surface long in a specific direction with the first optical system and the second optical system being arranged in the one surface in an orthogonal direction almost orthogonal to the specific direction. The first optical system and the second optical system are arranged such that an optical axis of the first optical system and an optical axis of the second optical system form an angle in the specific direction.
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12.发明申请公开(公告)号：US20160269633A1
公开(公告)日：2016-09-15
申请号：US15163373
申请日：2016-05-24
Applicant: Sony Corporation
Inventor： Minoru Ishida
CPC classification number: H04N5/23238 , G06T5/006 , G06T2207/20221 , H04N5/2252 , H04N5/2258 , H04N5/23219 , H04N5/23222 , H04N5/23235 , H04N5/23293
Abstract: An information processing apparatus includes a first optical system, a second optical system, and a casing. The first optical system is configured to input light into a first imaging device. The second optical system is configured to input light into a second imaging device. The casing includes one surface long in a specific direction with the first optical system and the second optical system being arranged in the one surface in an orthogonal direction almost orthogonal to the specific direction. The first optical system and the second optical system are arranged such that an optical axis of the first optical system and an optical axis of the second optical system form an angle in the specific direction.
Abstract translation: 信息处理装置包括第一光学系统，第二光学系统和外壳。 第一光学系统被配置为将光输入到第一成像装置中。 第二光学系统被配置为将光输入到第二成像装置中。 壳体包括在第一光学系统的特定方向上长的一个表面，并且第二光学系统沿着与特定方向几乎正交的正交方向在一个表面中布置。 第一光学系统和第二光学系统被布置成使得第一光学系统的光轴和第二光学系统的光轴在特定方向上形成一个角度。
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13.发明申请公开(公告)号：US20140347501A1
公开(公告)日：2014-11-27
申请号：US14278448
申请日：2014-05-15
Applicant: Sony Corporation
Inventor： Minoru Ishida
CPC classification number: H04N5/23238 , G06T5/006 , G06T2207/20221 , H04N5/2252 , H04N5/2258 , H04N5/23219 , H04N5/23222 , H04N5/23235 , H04N5/23293
Abstract: An information processing apparatus includes a first optical system, a second optical system, and a casing. The first optical system is configured to input light into a first imaging device. The second optical system is configured to input light into a second imaging device. The casing includes one surface long in a specific direction with the first optical system and the second optical system being arranged in the one surface in an orthogonal direction almost orthogonal to the specific direction. The first optical system and the second optical system are arranged such that an optical axis of the first optical system and an optical axis of the second optical system form an angle in the specific direction.
Abstract translation: 信息处理装置包括第一光学系统，第二光学系统和外壳。 第一光学系统被配置为将光输入到第一成像装置中。 第二光学系统被配置为将光输入到第二成像装置中。 壳体包括在第一光学系统的特定方向上长的一个表面，并且第二光学系统沿着与特定方向几乎正交的正交方向在一个表面中布置。 第一光学系统和第二光学系统被布置成使得第一光学系统的光轴和第二光学系统的光轴在特定方向上形成一个角度。
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公开(公告)号：US11973091B2
公开(公告)日：2024-04-30
申请号：US17148207
申请日：2021-01-13
Applicant: SONY CORPORATION
Inventor： Harumi Tanaka , Yoshiaki Masuda , Shinji Miyazawa , Minoru Ishida
IPC: H01L27/146 , G01N21/64 , G01N21/78 , H01L23/48 , H01L31/054 , H04N25/48 , H04N25/70
CPC classification number: H01L27/14605 , G01N21/64 , G01N21/78 , H01L23/481 , H01L27/14618 , H01L27/14632 , H01L27/14636 , H01L27/14685 , H01L27/14687 , H01L31/0543 , H04N25/48 , H04N25/70 , G01N21/6454 , G01N2021/6471 , H01L27/14621 , H01L27/14627 , H01L27/14634
Abstract: The present disclosure relates to reducing the size of a solid-state imaging apparatus. The solid-state imaging apparatus is configured by laminating a first structure body, comprising a pixel array unit in which pixels for performing photoelectric conversion are two-dimensionally aligned, and a second structure body, comprising an output circuit unit for outputting a pixel signal. The output circuit unit, including a through via which penetrates a semiconductor substrate constituting a part of the second structure body, and a signal output external terminal connected to the outside of the apparatus are arranged under the first structure body, the output circuit unit is connected to the signal output external terminal via the through via, and the outermost surface of the apparatus is a resin layer formed on an upper layer of an on-chip lens of the pixel array unit.
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公开(公告)号：US11527568B2
公开(公告)日：2022-12-13
申请号：US16080575
申请日：2017-02-24
Applicant: SONY CORPORATION
Inventor： Tomohiko Asatsuma , Minoru Ishida
IPC: H01L27/146
Abstract: Provided are a first photoelectric conversion unit, a second photoelectric conversion unit having a smaller electric charge amount to be converted per unit time than the first photoelectric conversion unit, a charge accumulation unit that accumulates an electric charge generated by the second photoelectric conversion unit, a charge voltage conversion unit, a first transfer gate unit that transfers an electric charge from the first photoelectric conversion unit to the charge voltage conversion unit, a second transfer gate unit that couples potentials of the charge voltage conversion unit and the charge accumulation unit, a third transfer gate unit that transfers an electric charge from the second photoelectric conversion unit to the charge accumulation unit, an overflow path formed under a gate electrode of the third transfer gate unit and transfers an electric charge overflowing from the second photoelectric conversion unit to the charge accumulation unit, and a light reducing unit that reduces light to enter the second photoelectric conversion unit.
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Patent Agency Ranking
公开(公告)号：US11342371B2
公开(公告)日：2022-05-24
申请号：US16945247
申请日：2020-07-31
Applicant: SONY CORPORATION
Inventor： Hiroyasu Matsugai , Hiroyuki Itou , Suguru Saito , Keiji Ohshima , Masanori Iwasaki , Toshihiko Hayashi , Shuzo Sato , Nobutoshi Fujii , Hiroshi Tazawa , Toshiaki Shiraiwa , Minoru Ishida
IPC: H01L27/146 , B29D11/00 , G02B13/00 , G02B1/11
Abstract: A deformation of a stacked lens is suppressed.
A stacked lens structure has a configuration in which substrates with lenses having a lens disposed on an inner side of a through-hole formed in the substrate are bonded and stacked by direct bonding. The present technique can be applied to a camera module or the like in which a stacked lens structure in which at least three substrates with lenses including first to third substrates with lenses which are substrates with lenses in which a through-hole is formed in the substrate and a lens is formed on an inner side of the through-hole is integrated with a light receiving element, for example.-
公开(公告)号：US10431618B2
公开(公告)日：2019-10-01
申请号：US15567289
申请日：2016-07-15
Applicant: SONY CORPORATION
Inventor： Hiroyasu Matsugai , Hiroyuki Itou , Suguru Saito , Keiji Ohshima , Masanori Iwasaki , Toshihiko Hayashi , Shuzo Sato , Nobutoshi Fujii , Hiroshi Tazawa , Toshiaki Shiraiwa , Minoru Ishida
IPC: H01L27/146 , B29D11/00 , G02B13/00 , G02B1/11
Abstract: A deformation of a stacked lens is suppressed. A stacked lens structure has a configuration in which substrates with lenses having a lens disposed on an inner side of a through-hole formed in the substrate are bonded and stacked by direct bonding. The present technique can be applied to a camera module or the like in which a stacked lens structure in which at least three substrates with lenses including first to third substrates with lenses which are substrates with lenses in which a through-hole is formed in the substrate and a lens is formed on an inner side of the through-hole is integrated with a light receiving element, for example.
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公开(公告)号：US09762797B2
公开(公告)日：2017-09-12
申请号：US14472642
申请日：2014-08-29
Applicant: SONY CORPORATION
Inventor： Minoru Ishida
CPC classification number: H04N5/23238 , H04M2250/52 , H04N5/225
Abstract: An imaging apparatus includes: an image generation section that generates at least one of a first captured image having a predetermined size and a second captured image having an aspect ratio different from that of the first captured image; a recording control section that, when an instruction operation to record the generated captured image is received, records the generated captured image based on the instruction operation; and a display control section that, when a captured image to be displayed at the time of displaying the recorded captured image on a display section is the second captured image, displays the second captured image and an enlarged image of a specific region in the second captured image are displayed on the display section in a correlated manner.
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公开(公告)号：US11056463B2
公开(公告)日：2021-07-06
申请号：US15528883
申请日：2015-12-11
Applicant: SONY CORPORATION
Inventor： Hiroshi Takahashi , Tomofumi Arakawa , Minoru Ishida
IPC: H01L21/768 , H01L23/48 , H01L23/528 , H01L25/10 , H01L23/485 , H01L25/065 , H01L25/18 , G11C5/00 , G11C29/00 , G11C5/02 , H01L25/07 , G06F12/00 , G11C7/16 , H01L27/146 , H04N5/378 , H01L25/11 , G11C5/06 , G11C7/10 , G11C8/10 , H01L27/118 , H03K19/0175 , H04N5/907 , H04N5/225 , H04N5/77 , H01L23/482 , H01L25/075 , H01L25/04
Abstract: The present technology relates to a semiconductor apparatus, a production method, and an electronic apparatus that enable semiconductor apparatuses to be laminated and the laminated semiconductor apparatuses to be identified. A semiconductor apparatus that is laminated and integrated with a plurality of semiconductor apparatuses, includes a first penetrating electrode for connecting with the other semiconductor apparatuses and a second penetrating electrode that connects the first penetrating electrode and an internal device, the second penetrating electrode being arranged at a position that differs for each of the laminated semiconductor apparatuses. The second penetrating electrode indicates a lamination position at a time of lamination. An address of each of the laminated semiconductor apparatuses in a lamination direction is identified by writing using external signals after lamination. The present technology is applicable to a memory chip and an FPGA chip.
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公开(公告)号：US10818717B2
公开(公告)日：2020-10-27
申请号：US16564444
申请日：2019-09-09
Applicant: SONY CORPORATION
Inventor： Hiroyasu Matsugai , Hiroyuki Itou , Suguru Saito , Keiji Ohshima , Masanori Iwasaki , Toshihiko Hayashi , Shuzo Sato , Nobutoshi Fujii , Hiroshi Tazawa , Toshiaki Shiraiwa , Minoru Ishida
IPC: H01L27/146 , B29D11/00 , G02B13/00 , G02B1/11
Abstract: A deformation of a stacked lens is suppressed.A stacked lens structure has a configuration in which substrates with lenses having a lens disposed on an inner side of a through-hole formed in the substrate are bonded and stacked by direct bonding. The present technique can be applied to a camera module or the like in which a stacked lens structure in which at least three substrates with lenses including first to third substrates with lenses which are substrates with lenses in which a through-hole is formed in the substrate and a lens is formed on an inner side of the through-hole is integrated with a light receiving element, for example.
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