公开(公告)号：US11688697B2

公开(公告)日：2023-06-27

申请号：US17662977

申请日：2022-05-11

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： Dong Won Son ,  Byeonghoon Kim ,  Sung Ho Choi ,  Sung Jae Lim ,  Jong Ho Shin ,  SungWon Cho ,  ChangOh Kim ,  KyoungHee Park

IPC: H01L23/552 ,  H01L23/31 ,  H01L23/367 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L23/552 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/367 ,  H01L23/49816 ,  H01L23/562 ,  H01L24/14 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/181 ,  H01L2924/3025

Abstract: A semiconductor device has a substrate and a semiconductor die disposed over the substrate. An encapsulant is deposited over the semiconductor die and substrate with a surface of the semiconductor die exposed from the encapsulant. A first shielding layer is formed over the semiconductor die. In some embodiments, the first shielding layer includes a stainless steel layer in contact with the surface of the semiconductor die and a copper layer formed over the stainless steel layer. The first shielding layer may further include a protective layer formed over the copper layer. One embodiment has a heatsink bonded to the semiconductor die through a solder layer. A second shielding layer can be formed over a side surface of the semiconductor die.

公开(公告)号：US11355452B2

公开(公告)日：2022-06-07

申请号：US17068482

申请日：2020-10-12

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： Dong Won Son ,  Byeonghoon Kim ,  Sung Ho Choi ,  Sung Jae Lim ,  Jong Ho Shin ,  SungWon Cho ,  ChangOh Kim ,  KyoungHee Park

IPC: H01L23/34 ,  H01L23/28 ,  H01L21/00 ,  H05K7/20 ,  H01L23/552 ,  H01L23/31 ,  H01L23/00 ,  H01L23/498 ,  H01L23/367

Abstract: A semiconductor device has a substrate and a semiconductor die disposed over the substrate. An encapsulant is deposited over the semiconductor die and substrate with a surface of the semiconductor die exposed from the encapsulant. A first shielding layer is formed over the semiconductor die. In some embodiments, the first shielding layer includes a stainless steel layer in contact with the surface of the semiconductor die and a copper layer formed over the stainless steel layer. The first shielding layer may further include a protective layer formed over the copper layer. One embodiment has a heatsink bonded to the semiconductor die through a solder layer. A second shielding layer can be formed over a side surface of the semiconductor die.

公开(公告)号：US20220157739A1

公开(公告)日：2022-05-19

申请号：US16950295

申请日：2020-11-17

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： HunTeak Lee ,  KyungHwan Kim ,  HeeSoo Lee ,  ChangOh Kim ,  KyoungHee Park ,  JinHee Jung ,  OMin Kwon ,  JiWon Lee ,  YuJeong Jang

IPC: H01L23/552 ,  H01L21/56

Abstract: A semiconductor package has a substrate, a first component disposed over the substrate, an encapsulant deposited over the first component, and a second component disposed over the substrate outside the encapsulant. A metal mask is disposed over the second component. A shielding layer is formed over the semiconductor package. The metal mask after forming the shielding layer. The shielding layer is optionally formed on a contact pad of the substrate while a conic area above the contact pad that extends 40 degrees from vertical remains free of the encapsulant and metal mask while forming the shielding layer. Surfaces of the metal mask and encapsulant oriented toward the contact pad can be sloped. The metal mask can be disposed and removed using a pick-and-place machine.

公开(公告)号：US11145603B2

公开(公告)日：2021-10-12

申请号：US16005387

申请日：2018-06-11

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： Byung Joon Han ,  Il Kwon Shim ,  KyoungHee Park ,  Yaojian Lin ,  KyoWang Koo ,  In Sang Yoon ,  SeungYong Chai ,  SungWon Cho ,  SungSoo Kim ,  Hun Teak Lee ,  DeokKyung Yang

IPC: H01L23/00 ,  H01L23/552 ,  H01L23/498 ,  H01L21/48 ,  H01L21/683 ,  H01L23/31 ,  H01L25/16 ,  H01L21/56

Abstract: An integrated circuit packaging system and method of manufacture thereof includes: a substrate with internal circuitry between a substrate top side, a substrate bottom side, and vertical sides; an integrated circuit coupled to the internal circuitry; a molded package body formed directly on the integrated circuit and the substrate top side of the substrate; and a conductive conformal shield structure applied directly on the molded package body, the vertical sides, and to extend below the substrate bottom side coupled to the internal circuitry.

公开(公告)号：US10804217B2

公开(公告)日：2020-10-13

申请号：US16529486

申请日：2019-08-01

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： SungWon Cho ,  ChangOh Kim ,  Il Kwon Shim ,  InSang Yoon ,  KyoungHee Park

IPC: H01L27/14 ,  H01L21/00 ,  H01L23/552 ,  H01L23/00 ,  H01L23/36 ,  H01L23/522 ,  H01L23/50 ,  H01L23/60 ,  H01L23/498 ,  H01L27/02 ,  H01L23/31

Abstract: A semiconductor device has a substrate and a semiconductor die disposed over the substrate. An encapsulant is deposited over the semiconductor die and substrate with a surface of the semiconductor die exposed from the encapsulant. A first shielding layer is formed over the semiconductor die. In some embodiments, the first shielding layer includes a stainless steel layer in contact with the surface of the semiconductor die and a copper layer formed over the stainless steel layer. The first shielding layer may further include a protective layer formed over the copper layer. One embodiment has a heatsink bonded to the semiconductor die through a solder layer. A second shielding layer can be formed over a side surface of the semiconductor die.

公开(公告)号：US10134664B2

公开(公告)日：2018-11-20

申请号：US15433866

申请日：2017-02-15

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： MinKyung Kang ,  YoungDal Roh ,  Dong Ju Jeon ,  KyoungHee Park

IPC: H01L23/49 ,  H01L21/50 ,  H01L23/498 ,  H01L21/48 ,  H01L23/00

Abstract: An integrated circuit packaging system and method of manufacture thereof includes: a dielectric core having an embedded pad; a top solder resist layer on the dielectric core, a pad top surface of the embedded pad below the top solder resist layer; a device interconnect attached to the embedded pad; and an integrated circuit device having an interconnect pillar, the interconnect pillar attached to the device interconnect for mounting the integrated circuit device to the dielectric core.

公开(公告)号：US12266615B2

公开(公告)日：2025-04-01

申请号：US18174790

申请日：2023-02-27

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： ChangOh Kim ,  KyoungHee Park ,  JinHee Jung ,  OMin Kwon ,  JiWon Lee ,  YuJeong Jang

IPC: H01L23/552 ,  H01L21/033 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31

Abstract: A semiconductor device has a semiconductor package including a substrate comprising a land grid array. A component is disposed over the substrate. An encapsulant is deposited over the component. The land grid array remains outside the encapsulant. A fanged metal mask is disposed over the land grid array. A shielding layer is formed over the semiconductor package. The fanged metal mask is removed after forming the shielding layer.

公开(公告)号：US20250023227A1

公开(公告)日：2025-01-16

申请号：US18902287

申请日：2024-09-30

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： HunTeak Lee ,  KyoungHee Park ,  KyungHwan Kim ,  SeungHyun Lee ,  SangJun Park

IPC: H01Q1/22 ,  H01L21/56 ,  H01L23/31 ,  H01L23/36 ,  H01L23/498 ,  H01L23/552 ,  H01L25/16 ,  H01R12/71 ,  H05K1/18 ,  H05K3/34

Abstract: A semiconductor device has a PCB with an antenna and a semiconductor package mounted onto the PCB. An epoxy molding compound bump is formed or disposed over the PCB opposite the semiconductor package. A first shielding layer is formed over the PCB. A second shielding layer is formed over the semiconductor package. A board-to-board (B2B) connector is disposed on the PCB or as part of the semiconductor package. A conductive bump is disposed between the semiconductor package and PCB.

公开(公告)号：US11862572B2

公开(公告)日：2024-01-02

申请号：US18161693

申请日：2023-01-30

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： ChangOh Kim ,  KyoungHee Park ,  SeongHwan Park ,  JinHee Jung

IPC: H01L23/552 ,  H01L23/66 ,  H01L21/56 ,  H01L23/31 ,  H01L21/48 ,  H01Q1/22

CPC classification number: H01L23/552 ,  H01L21/486 ,  H01L21/56 ,  H01L23/31 ,  H01L23/66 ,  H01Q1/2283

Abstract: A semiconductor device has a first package layer. A first shielding layer is formed over the first package layer. The first shielding layer is patterned to form a redistribution layer. An electrical component is disposed over the redistribution layer. An encapsulant is deposited over the electrical component. A second shielding layer is formed over the encapsulant. The second shielding layer is patterned. The patterning of the first shielding layer and second shielding layer can be done with a laser. The second shielding layer can be patterned to form an antenna.

公开(公告)号：US11664327B2

公开(公告)日：2023-05-30

申请号：US16950295

申请日：2020-11-17

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： HunTeak Lee ,  KyungHwan Kim ,  HeeSoo Lee ,  ChangOh Kim ,  KyoungHee Park ,  JinHee Jung ,  OMin Kwon ,  JiWon Lee ,  YuJeong Jang

IPC: H01L23/552 ,  H01L21/56 ,  H01L23/498

CPC classification number: H01L23/552 ,  H01L21/56 ,  H01L21/561 ,  H01L21/568 ,  H01L23/49822

Abstract: A semiconductor package has a substrate, a first component disposed over the substrate, an encapsulant deposited over the first component, and a second component disposed over the substrate outside the encapsulant. A metal mask is disposed over the second component. A shielding layer is formed over the semiconductor package. The metal mask after forming the shielding layer. The shielding layer is optionally formed on a contact pad of the substrate while a conic area above the contact pad that extends 40 degrees from vertical remains free of the encapsulant and metal mask while forming the shielding layer. Surfaces of the metal mask and encapsulant oriented toward the contact pad can be sloped. The metal mask can be disposed and removed using a pick-and-place machine.