公开(公告)号：US20230154864A1

公开(公告)日：2023-05-18

申请号：US18155878

申请日：2023-01-18

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： DeokKyung Yang ,  HunTeak Lee ,  HeeSoo Lee ,  Wanil Lee ,  SangDuk Lee

IPC: H01L23/552 ,  H01L23/31 ,  H01L21/56 ,  H01L23/66

CPC classification number: H01L23/552 ,  H01L23/3107 ,  H01L21/568 ,  H01L23/66 ,  H01L2223/6677

Abstract: A semiconductor device has a substrate comprising a carrier and an interposer disposed on the carrier. An electrical component is disposed over a first surface of the interposer. An interconnect structure is disposed over the first surface of the interposer. An encapsulant is deposited over the electrical component, interconnect structure, and substrate. A trench is formed through the encapsulant and interposer into the carrier. A shielding layer is formed over the encapsulant and into the trench. The carrier is removed after forming the shielding layer.

公开(公告)号：US11145603B2

公开(公告)日：2021-10-12

申请号：US16005387

申请日：2018-06-11

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： Byung Joon Han ,  Il Kwon Shim ,  KyoungHee Park ,  Yaojian Lin ,  KyoWang Koo ,  In Sang Yoon ,  SeungYong Chai ,  SungWon Cho ,  SungSoo Kim ,  Hun Teak Lee ,  DeokKyung Yang

IPC: H01L23/00 ,  H01L23/552 ,  H01L23/498 ,  H01L21/48 ,  H01L21/683 ,  H01L23/31 ,  H01L25/16 ,  H01L21/56

Abstract: An integrated circuit packaging system and method of manufacture thereof includes: a substrate with internal circuitry between a substrate top side, a substrate bottom side, and vertical sides; an integrated circuit coupled to the internal circuitry; a molded package body formed directly on the integrated circuit and the substrate top side of the substrate; and a conductive conformal shield structure applied directly on the molded package body, the vertical sides, and to extend below the substrate bottom side coupled to the internal circuitry.

公开(公告)号：US10797039B2

公开(公告)日：2020-10-06

申请号：US15976455

申请日：2018-05-10

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： DeokKyung Yang ,  OhHan Kim ,  HeeSoo Lee ,  HunTeak Lee ,  InSang Yoon ,  Il Kwon Shim

IPC: H01L25/00 ,  H01L23/00 ,  H01L21/56 ,  H01L23/552 ,  H01L25/065 ,  H01L25/16 ,  H01L23/498 ,  H01L23/31 ,  H01L23/538 ,  H01L23/50

Abstract: A semiconductor device has a first substrate and a second substrate. An opening is formed through the second substrate. A first semiconductor component and second semiconductor component are disposed between the first substrate and second substrate. The second substrate is electrically coupled to the first substrate through the first semiconductor component. A first terminal of the first semiconductor component is electrically coupled to the first substrate. A second terminal of the first semiconductor component is electrically coupled to the second substrate. The second semiconductor component extends into the opening. An encapsulant is deposited over the first substrate and second substrate.

公开(公告)号：US20200161252A1

公开(公告)日：2020-05-21

申请号：US16193691

申请日：2018-11-16

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： DeokKyung Yang ,  HunTeak Lee ,  HeeSoo Lee ,  Wanil Lee ,  SangDuk Lee

IPC: H01L23/552 ,  H01L23/31 ,  H01L23/66 ,  H01L21/56

Abstract: A semiconductor device has a substrate comprising a carrier and an interposer disposed on the carrier. An electrical component is disposed over a first surface of the interposer. An interconnect structure is disposed over the first surface of the interposer. An encapsulant is deposited over the electrical component, interconnect structure, and substrate. A trench is formed through the encapsulant and interposer into the carrier. A shielding layer is formed over the encapsulant and into the trench. The carrier is removed after forming the shielding layer.

公开(公告)号：US20180269181A1

公开(公告)日：2018-09-20

申请号：US15458649

申请日：2017-03-14

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： DeokKyung Yang ,  YongMin Kim ,  JaeHyuk Choi ,  YeoChan Ko ,  HeeSoo Lee

IPC: H01L25/065 ,  H01L21/56 ,  H01L23/00 ,  H01L25/00 ,  H01L23/552 ,  H01L23/498 ,  H01L23/31 ,  H01L21/78 ,  H01L21/66 ,  H01L21/683 ,  H01L23/538 ,  H01L25/10 ,  H01L21/48

CPC classification number: H01L25/0655 ,  H01L21/486 ,  H01L21/56 ,  H01L21/561 ,  H01L21/565 ,  H01L21/566 ,  H01L21/6835 ,  H01L22/14 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/50 ,  H01L23/5384 ,  H01L23/552 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/81 ,  H01L24/94 ,  H01L25/0652 ,  H01L25/16 ,  H01L25/50 ,  H01L2221/68331 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2221/68381 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/05111 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16113 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81201 ,  H01L2224/81203 ,  H01L2224/81411 ,  H01L2224/81424 ,  H01L2224/81439 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/81466 ,  H01L2224/81484 ,  H01L2224/81815 ,  H01L2224/92125 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06517 ,  H01L2225/06537 ,  H01L2225/06572 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/18161 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/19106 ,  H01L2924/3025 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00014 ,  H01L2924/013 ,  H01L2924/014 ,  H01L2924/01082

Abstract: A semiconductor device includes a substrate with an opening formed through the substrate. A first electronic component is disposed over the substrate outside a footprint of the first opening. A second electronic component is disposed over the substrate opposite the first electrical component. A third electronic component is disposed over the substrate adjacent to the first electronic component. The substrate is disposed in a mold including a second opening of the mold over a first side of the substrate. The mold contacts the substrate between the first electronic component and the third electronic component. An encapsulant is deposited into the second opening. The encapsulant flows through the first opening to cover a second side of the substrate. In some embodiments, a mold film is disposed in the mold, and an interconnect structure on the substrate is embedded in the mold film.

公开(公告)号：US20180158768A1

公开(公告)日：2018-06-07

申请号：US15830644

申请日：2017-12-04

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： OhHan Kim ,  DeokKyung Yang ,  HunTeak Lee ,  InSang Yoon ,  Il Kwon Shim

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L23/552 ,  H01L25/065 ,  H01L23/538 ,  H01L21/56 ,  H01L21/48

CPC classification number: H01L23/49838 ,  H01L21/4803 ,  H01L21/4846 ,  H01L21/56 ,  H01L21/561 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/5385 ,  H01L23/552 ,  H01L24/16 ,  H01L24/81 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/162 ,  H01L2224/0401 ,  H01L2224/05111 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/11334 ,  H01L2224/1146 ,  H01L2224/13023 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/48091 ,  H01L2224/48179 ,  H01L2224/73265 ,  H01L2224/81815 ,  H01L2224/97 ,  H01L2924/15151 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19102 ,  H01L2924/19105 ,  Y02P80/30

Abstract: A semiconductor device has a first substrate. A first semiconductor component and second semiconductor component are disposed on the first substrate. In some embodiments, a recess is formed in the first substrate, and the first semiconductor component is disposed on the recess of the first substrate. A second substrate has an opening formed through the second substrate. A third semiconductor component is disposed on the second substrate. The second substrate is disposed over the first substrate and second semiconductor component. The first semiconductor component extends through the opening. An encapsulant is deposited over the first substrate and second substrate.

公开(公告)号：US11587882B2

公开(公告)日：2023-02-21

申请号：US17163776

申请日：2021-02-01

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： DeokKyung Yang ,  HunTeak Lee ,  HeeSoo Lee ,  Wanil Lee ,  SangDuk Lee

IPC: H01L23/552 ,  H01L23/31 ,  H01L21/56 ,  H01L23/66

Abstract: A semiconductor device has a substrate comprising a carrier and an interposer disposed on the carrier. An electrical component is disposed over a first surface of the interposer. An interconnect structure is disposed over the first surface of the interposer. An encapsulant is deposited over the electrical component, interconnect structure, and substrate. A trench is formed through the encapsulant and interposer into the carrier. A shielding layer is formed over the encapsulant and into the trench. The carrier is removed after forming the shielding layer.

公开(公告)号：US11342294B2

公开(公告)日：2022-05-24

申请号：US16821093

申请日：2020-03-17

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： DeokKyung Yang ,  HunTeak Lee ,  OhHan Kim ,  HeeSoo Lee ,  DaeHyeok Ha ,  Wanil Lee

IPC: H01L23/00 ,  H01L23/538 ,  H01L23/31

Abstract: A semiconductor device has a first substrate and a semiconductor die disposed over the first substrate. A second substrate has a multi-layered conductive post. The conductive post has a first conductive layer and a second conductive layer formed over the first conductive layer. The first conductive layer is wider than the second conductive layer. A portion of the conductive post can be embedded within the second substrate. The second substrate is disposed over the first substrate adjacent to the semiconductor die. An encapsulant is deposited around the second substrate and semiconductor die. An opening is formed in the second substrate aligned with the conductive post. An interconnect structure is formed in the opening to contact the conductive post. A discrete electrical component is disposed over a surface of the first substrate opposite the semiconductor die. A shielding layer is formed over the discrete electrical component.

公开(公告)号：US10790268B2

公开(公告)日：2020-09-29

申请号：US16821202

申请日：2020-03-17

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： DeokKyung Yang ,  HunTeak Lee ,  HeeSoo Lee

IPC: H01L23/552 ,  H01L25/10 ,  H01L25/00 ,  H01L23/538 ,  H01L21/48 ,  H01L23/00 ,  H01L21/56 ,  H01L23/31

Abstract: A semiconductor device has a first substrate and a semiconductor die disposed over the first substrate. A conductive pillar is formed on the first substrate. A first encapsulant is deposited over the first substrate and semiconductor die after forming the conductive pillar. A groove is formed in the first encapsulant around the conductive pillar. A first passive device is disposed over a second substrate. A second encapsulant is deposited over the first passive device and second substrate. The first substrate is mounted over the second substrate. A shielding layer is formed over the second encapsulant. A second passive device can be mounted over the second substrate opposite the first passive device and outside a footprint of the first substrate.

公开(公告)号：US20200219859A1

公开(公告)日：2020-07-09

申请号：US16821202

申请日：2020-03-17

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： DeokKyung Yang ,  HunTeak Lee ,  HeeSoo Lee

IPC: H01L25/10 ,  H01L25/00 ,  H01L23/538 ,  H01L23/552 ,  H01L21/48 ,  H01L23/00 ,  H01L21/56

Abstract: A semiconductor device has a first substrate and a semiconductor die disposed over the first substrate. A conductive pillar is formed on the first substrate. A first encapsulant is deposited over the first substrate and semiconductor die after forming the conductive pillar. A groove is formed in the first encapsulant around the conductive pillar. A first passive device is disposed over a second substrate. A second encapsulant is deposited over the first passive device and second substrate. The first substrate is mounted over the second substrate. A shielding layer is formed over the second encapsulant. A second passive device can be mounted over the second substrate opposite the first passive device and outside a footprint of the first substrate.