公开(公告)号：US20150303282A1

公开(公告)日：2015-10-22

申请号：US14788737

申请日：2015-06-30

Applicant: STMICROELECTRONICS, INC.

Inventor： PIERRE MORIN ,  NICOLAS LOUBET

IPC: H01L29/66

CPC classification number: H01L27/0924 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7843 ,  H01L29/7848 ,  H01L29/7849 ,  H01L29/785

Abstract: Methods and structures for forming strained-channel finFETs are described. Fin structures for finFETs may be formed using two epitaxial layers of different lattice constants that are grown over a bulk substrate. A first thin, strained, epitaxial layer may be cut to form strain-relieved base structures for fins. The base structures may be constrained in a strained-relieved state. Fin structures may be epitaxially grown in a second layer over the base structures. The constrained base structures can cause higher amounts of strain to form in the epitaxially-grown fins than would occur for non-constrained base structures.

Abstract translation: 描述形成应变通道鳍状FET的方法和结构。 可以使用在体基板上生长的不同晶格常数的两个外延层来形成finFET的鳍结构。 可以切割第一薄的应变外延层以形成用于翅片的应变消除的基础结构。 基础结构可以被约束在应变消除状态。 翅片结构可以在基底结构上的第二层中外延生长。 受限的碱基结构可以在外延生长的翅片中形成比在非约束基础结构中发生的更大量的应变。

公开(公告)号：US20150255457A1

公开(公告)日：2015-09-10

申请号：US14196596

申请日：2014-03-04

Applicant: STMicroelectronics, Inc. ,  International Business Machines Corporation

Inventor： NICOLAS LOUBET ,  Hong He ,  James Kuss

IPC: H01L27/088 ,  H01L29/16 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L27/0886 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: Methods and structures for forming finFETs of different semiconductor composition and of different conductivity type on a same wafer are described. Some finFET structures may include strained channel regions. FinFETs of a first semiconductor composition may be grown in trenches formed in a second semiconductor composition. Material of the second semiconductor composition may be removed from around some of the fins at first regions of the wafer, and may remain around fins at second regions of the wafer. A chemical component from the second semiconductor composition may be driven into the fins by diffusion at the second regions to form finFETs of a different chemical composition from those of the first regions. The converted fins at the second regions may include strain.

Abstract translation: 描述了在同一晶片上形成不同半导体组成和不同导电类型的finFET的方法和结构。 一些finFET结构可以包括应变通道区域。 可以在第二半导体组合物中形成的沟槽中生长第一半导体组合物的FinFET。 第二半导体组合物的材料可以从晶片的第一区域周围的一些鳍片周围去除，并且可以保留在晶片的第二区域周围的鳍片周围。 来自第二半导体组合物的化学成分可以通过在第二区域的扩散而被驱入散热片，以形成与第一区域不同的化学组成的finFET。 在第二区域处的转换的翅片可以包括应变。

公开(公告)号：US20150200205A1

公开(公告)日：2015-07-16

申请号：US14668482

申请日：2015-03-25

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  STMicroelectronics, Inc. ,  GLOBALFOUNDRIES Inc.

Inventor： KANGGUO CHENG ,  BRUCE B. DORIS ,  ALI KHAKIFIROOZ ,  QING LIU ,  NICOLAS LOUBET ,  SCOTT LUNING

IPC: H01L27/12 ,  H01L29/10

CPC classification number: H01L21/845 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/84 ,  H01L27/092 ,  H01L27/0922 ,  H01L27/0924 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/161 ,  H01L29/4966

Abstract: A method for semiconductor fabrication includes providing channel regions on a substrate including at least one Silicon Germanium (SiGe) channel region, the substrate including a plurality of regions including a first region and a second region. Gate structures are formed for a first n-type field effect transistor (NFET) and a first p-type field effect transistor (PFET) in the first region and a second NFET and a second PFET in the second region, the gate structure for the first PFET being formed on the SiGe channel region. The gate structure for the first NFET includes a gate material having a first work function and the gate structures for the first PFET, second NFET and second PFET include a gate material having a second work function such that multi-threshold voltage devices are provided.

Abstract translation: 一种用于半导体制造的方法包括在包括至少一个硅锗（SiGe）沟道区的衬底上提供沟道区，所述衬底包括包括第一区和第二区的多个区域。 对于第一区域中的第一n型场效应晶体管（NFET）和第一p型场效应晶体管（PFET）以及第二区域中的第二NFET和第二PFET形成栅极结构， 第一PFET形成在SiGe沟道区上。 用于第一NFET的栅极结构包括具有第一功函数的栅极材料，并且用于第一PFET，第二NFET和第二PFET的栅极结构包括具有第二功函数的栅极材料，使得提供多阈值电压器件。

公开(公告)号：US20170179137A1

公开(公告)日：2017-06-22

申请号：US15448626

申请日：2017-03-03

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  STMICROELECTRONICS, INC.

Inventor： STEPHANE ALLEGRET-MARET ,  KANGGUO CHENG ,  BRUCE DORIS ,  PRASANNA KHARE ,  QING LIU ,  NICOLAS LOUBET

IPC: H01L27/11 ,  H01L29/08 ,  H01L29/417 ,  H01L21/3065 ,  H01L29/06 ,  H01L27/12 ,  H01L21/02 ,  H01L29/165 ,  H01L21/311 ,  H01L29/66 ,  H01L21/265 ,  H01L21/84 ,  H01L21/8238 ,  H01L21/762

CPC classification number: H01L27/092 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02532 ,  H01L21/26513 ,  H01L21/3065 ,  H01L21/31111 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/1104 ,  H01L27/1116 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/41783 ,  H01L29/6656 ,  H01L29/66772 ,  H01L29/78654

Abstract: An improved transistor with channel epitaxial silicon. In one aspect, a method of fabrication includes: forming a gate stack structure on an epitaxial silicon region disposed on a substrate, a width dimension of the epitaxial silicon region approximating a width dimension of the gate stack structure; and growing a raised epitaxial source and drain from the substrate, the raised epitaxial source and drain in contact with the epitaxial silicon region and the gate stack structure. For a SRAM device, further: removing an epitaxial layer in contact with the silicon substrate and the raised source and drain and to which the epitaxial silicon region is coupled leaving a space above the silicon substrate and under the raised epitaxial source and drain; and filling the space with an insulating layer and isolating the raised epitaxial source and drain and a channel of the transistor from the silicon substrate.

公开(公告)号：US20160111338A1

公开(公告)日：2016-04-21

申请号：US14969393

申请日：2015-12-15

Applicant: STMICROELECTRONICS, INC.

Inventor： NICOLAS LOUBET ,  PRASANNA KHARE ,  QING LIU

IPC: H01L21/8238 ,  H01L21/308 ,  H01L21/3065

CPC classification number: H01L21/823807 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0922

Abstract: A method for co-integrating finFETs of two semiconductor material types, e.g., Si and SiGe, on a bulk substrate is described. Fins for finFETs may be formed in an epitaxial layer of a first semiconductor type, and covered with an insulator. A portion of the fins may be removed to form voids in the insulator, and the voids may be filled by epitaxially growing a semiconductor material of a second type in the voids. The co-integrated finFETs may be formed at a same device level.

Abstract translation: 描述了用于在体基板上将诸如Si和SiGe的两种半导体材料类型的finFET共集成的方法。 用于finFET的鳍可以形成在第一半导体类型的外延层中，并被绝缘体覆盖。 可以去除一部分翅片以在绝缘体中形成空隙，并且可以通过在空隙中外延生长第二类型的半导体材料来填充空隙。 共同集成的finFET可以形成在相同的器件级。

公开(公告)号：US20160093639A1

公开(公告)日：2016-03-31

申请号：US14964648

申请日：2015-12-10

Applicant: STMICROELECTRONICS, INC.

Inventor： PIERRE MORIN ,  QING LIU ,  NICOLAS LOUBET

IPC: H01L27/12 ,  H01L29/161 ,  H01L29/16 ,  H01L27/092 ,  H01L29/06

CPC classification number: H01L27/1203 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/092 ,  H01L29/0649 ,  H01L29/16 ,  H01L29/161

Abstract: A method for making a semiconductor device may include forming, on a first semiconductor layer of a semiconductor-on-insulator (SOI) wafer, a second semiconductor layer comprising a second semiconductor material different than a first semiconductor material of the first semiconductor layer. The method may further include performing a thermal treatment in a non-oxidizing atmosphere to diffuse the second semiconductor material into the first semiconductor layer, and removing the second semiconductor layer.

公开(公告)号：US20150303285A1

公开(公告)日：2015-10-22

申请号：US14748270

申请日：2015-06-24

Applicant: STMICROELECTRONICS, INC.

Inventor： QING LIU ,  PRASANNA KHARE ,  NICOLAS LOUBET

IPC: H01L29/66 ,  H01L21/225 ,  H01L29/417

CPC classification number: H01L27/0886 ,  H01L21/2253 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/2658 ,  H01L21/26586 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/845 ,  H01L29/0847 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/785

Abstract: A multi-fin FINFET device may include a substrate and a plurality of semiconductor fins extending upwardly from the substrate and being spaced apart along the substrate. Each semiconductor fin may have opposing first and second ends and a medial portion therebetween, and outermost fins of the plurality of semiconductor fins may comprise an epitaxial growth barrier on outside surfaces thereof. The FINFET may further include at least one gate overlying the medial portions of the semiconductor fins, a plurality of raised epitaxial semiconductor source regions between the semiconductor fins adjacent the first ends thereof, and a plurality of raised epitaxial semiconductor drain regions between the semiconductor fins adjacent the second ends thereof.

Abstract translation: 多鳍FINFET器件可以包括衬底和从衬底向上延伸并沿着衬底间隔开的多个半导体鳍片。 每个半导体鳍片可以具有相对的第一和第二端以及它们之间的中间部分，并且多个半导体鳍片的最外面的鳍片可以在其外表面上包括外延生长阻挡层。 FINFET还可以包括覆盖半导体鳍片的中间部分的至少一个栅极，在与其第一端相邻的半导体鳍片之间的多个凸起的外延半导体源极区域和在相邻的半导体鳍片之间的多个凸起的外延半导体漏极区域 其第二端。

公开(公告)号：US20150236051A1

公开(公告)日：2015-08-20

申请号：US14182632

申请日：2014-02-18

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  STMICROELECTRONICS, INC.

Inventor： NICOLAS LOUBET ,  James KUSS

IPC: H01L27/12 ,  H01L21/02 ,  H01L29/165 ,  H01L29/06 ,  H01L21/84 ,  H01L29/16

CPC classification number: H01L27/1211 ,  H01L21/02236 ,  H01L21/02255 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/02639 ,  H01L21/02664 ,  H01L21/84 ,  H01L21/845 ,  H01L27/1203 ,  H01L29/0673 ,  H01L29/16 ,  H01L29/165 ,  H01L29/66439 ,  H01L29/78696

Abstract: A method for making a semiconductor device may include forming, above a substrate, a stack of alternating layers of first and second semiconductor materials. The second semiconductor material may be different than the first semiconductor material. The method may further include forming fins from the stack, with each fin having alternating layers of the first and second semiconductor materials, and selectively removing sidewall portions of the second semiconductor material from the fins to define recesses therein. The method may also include forming a dielectric material within the recesses, forming additional first semiconductor material on sidewall portions of the first semiconductor material in the fins, and forming a dielectric layer overlying the fins to define nanowires including the first semiconductor material within the dielectric layer.

Abstract translation: 制造半导体器件的方法可以包括在衬底之上形成第一和第二半导体材料的交替层叠。 第二半导体材料可以不同于第一半导体材料。 该方法还可以包括从堆叠形成翅片，其中每个翅片具有第一和第二半导体材料的交替层，并且从翅片选择性地去除第二半导体材料的侧壁部分以在其中限定凹部。 该方法还可以包括在凹槽内形成介电材料，在鳍片中的第一半导体材料的侧壁部分上形成附加的第一半导体材料，以及形成覆盖鳍片的介电层，以限定纳米线，该纳米线包括介电层内的第一半导体材料 。

公开(公告)号：US20140312423A1

公开(公告)日：2014-10-23

申请号：US13865795

申请日：2013-04-18

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  STMICROELECTRONICS, INC. ,  GLOBALFOUNDRIES INC.

Inventor： KANGGUO CHENG ,  BRUCE B. DORIS ,  ALI KHAKIFIROOZ ,  QING LIU ,  NICOLAS LOUBET ,  SCOTT LUNING

IPC: H01L27/12 ,  H01L21/8238

CPC classification number: H01L21/845 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/84 ,  H01L27/092 ,  H01L27/0922 ,  H01L27/0924 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/161 ,  H01L29/4966

Abstract: A method for semiconductor fabrication includes providing channel regions on a substrate including at least one Silicon Germanium (SiGe) channel region, the substrate including a plurality of regions including a first region and a second region. Gate structures are formed for a first n-type field effect transistor (NFET) and a first p-type field effect transistor (PFET) in the first region and a second NFET and a second PFET in the second region, the gate structure for the first PFET being formed on the SiGe channel region. The gate structure for the first NFET includes a gate material having a first work function and the gate structures for the first PFET, second NFET and second PFET include a gate material having a second work function such that multi-threshold voltage devices are provided.

Abstract translation: 一种用于半导体制造的方法包括在包括至少一个硅锗（SiGe）沟道区的衬底上提供沟道区，所述衬底包括包括第一区和第二区的多个区域。 对于第一区域中的第一n型场效应晶体管（NFET）和第一p型场效应晶体管（PFET）以及第二区域中的第二NFET和第二PFET形成栅极结构， 第一PFET形成在SiGe沟道区上。 用于第一NFET的栅极结构包括具有第一功函数的栅极材料，并且用于第一PFET，第二NFET和第二PFET的栅极结构包括具有第二功函数的栅极材料，使得提供多阈值电压器件。