公开(公告)号：US09244236B2

公开(公告)日：2016-01-26

申请号：US14802504

申请日：2015-07-17

Applicant: STMicroelectronics, Inc.

Inventor： John Hongguang Zhang

IPC: G02B6/42 ,  G02B6/43 ,  G02B6/122 ,  G02B6/124 ,  G02B6/132 ,  G02B6/136 ,  G02B6/12

CPC classification number: G02B6/43 ,  G02B6/122 ,  G02B6/124 ,  G02B6/132 ,  G02B6/136 ,  G02B6/42 ,  G02B6/4214 ,  G02B2006/12102

Abstract: A photonic integrated circuit includes optical circuitry fabricated over an underlying circuitry layer. The optical circuitry includes a dielectric material having recesses disposed within, layers of a light waveguide material deposited within the recesses, and lenses disposed over each layer of waveguide material. The underlying circuitry layer may include, for example, a semiconductor wafer as well as circuitry fabricated during front end of line (FEOL) semiconductor manufacturing such as, for example, sources, gates, drains, interconnects, contacts, resistors, and other circuitry that may be manufactured during FEOL processes. The underlying circuitry layer may also include circuitry manufactured during back end of line semiconductor manufacturing processes such as, for example, interconnect structures, metallization layers, and contacts.

Abstract translation: 光子集成电路包括在底层电路层上制造的光电路。 光学电路包括具有设置在沉积在凹部内的光波导材料的层内的凹槽的介电材料和设置在每层波导材料上的透镜。 底层电路层可以包括例如半导体晶片以及在前端（FEOL）半导体制造期间制造的电路，例如源，栅极，漏极，互连，触点，电阻器和其他电路，其中 可以在FEOL过程中制造。 底层电路层还可以包括在线半导体制造工艺的后端制造的电路，例如互连结构，金属化层和触点。

公开(公告)号：US20150357477A1

公开(公告)日：2015-12-10

申请号：US14298000

申请日：2014-06-06

Applicant: STMicroelectronics, Inc.

Inventor： John Hongguang Zhang ,  Walter Kleemeier

IPC: H01L29/786 ,  H01L27/12

CPC classification number: H01L29/41766 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/41733 ,  H01L29/4975 ,  H01L29/78603 ,  H01L29/78648

Abstract: An integrated circuit transistor is formed on and in a substrate. A trench in the substrate is at least partially filed with a metal material to form a source (or drain) contact buried in the substrate. The substrate further includes a source (or drain) region epitaxially grown above the source (or drain) contact. The substrate further includes a channel region adjacent to the source (or drain) region. A gate dielectric is provided on top of the channel region and a gate electrode is provided on top of the gate dielectric. The substrate is preferably of the silicon on insulator (SOI) type.

Abstract translation: 集成电路晶体管形成在衬底上和衬底中。 衬底中的沟槽至少部分地与金属材料填充以形成埋在衬底中的源极（或漏极）接触。 衬底还包括在源极（或漏极）触点上方外延生长的源极（或漏极）区域。 衬底还包括与源极（或漏极）区域相邻的沟道区域。 栅极电介质设置在沟道区域的顶部，栅电极设置在栅极电介质的顶部。 衬底优选为绝缘体上硅（SOI）型。

公开(公告)号：US20150311113A1

公开(公告)日：2015-10-29

申请号：US14264803

申请日：2014-04-29

Applicant: STMicroelectronics, Inc. ,  International Business Machines Corporation

Inventor： John Hongguang Zhang ,  Lawrence A. Clevenger ,  Carl Radens ,  Yiheng Xu ,  Richard Stephen Wise

IPC: H01L21/768 ,  H01L23/528

CPC classification number: H01L21/76816 ,  H01L21/0337 ,  H01L21/31144 ,  H01L23/5228 ,  H01L23/5283 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit includes a substrate with an interlevel dielectric layer positioned above the substrate. First trenches having a first depth are formed in the interlevel dielectric layer and a metal material fills the first trenches to form first interconnection lines. Second trenches having a second depth are also formed in the interlevel dielectric layer and filled with a metal material to form second interconnection lines. The first and second interconnection lines have a substantially equal pitch, which in a preferred implementation is a sub-lithographic pitch, and different resistivities due to the difference in trench depth. The first and second trenches are formed with an etching process through a hard mask having corresponding first and second openings of different depths. A sidewall image transfer process is used to define sub-lithographic structures for forming the first and second openings in the hard mask.

Abstract translation: 集成电路包括具有位于衬底上方的层间电介质层的衬底。 具有第一深度的第一沟槽形成在层间电介质层中，并且金属材料填充第一沟槽以形成第一互连线。 具有第二深度的第二沟槽也形成在层间电介质层中并且填充有金属材料以形成第二互连线。 第一和第二互连线具有基本相等的间距，其优选实施方式是亚光刻间距，以及由于沟槽深度的不同导致的不同的电阻率。 第一和第二沟槽通过具有不同深度的对应的第一和第二开口的硬掩模的蚀刻工艺形成。 侧壁图像转印过程用于限定用于在硬掩模中形成第一和第二开口的亚光刻结构。

公开(公告)号：US10892281B2

公开(公告)日：2021-01-12

申请号：US16713106

申请日：2019-12-13

Applicant: STMicroelectronics, Inc.

Inventor： John Hongguang Zhang

IPC: H01L27/12 ,  H01L29/08 ,  H01L29/06 ,  H01L21/762 ,  H01L21/02 ,  H01L29/161 ,  H01L29/20 ,  H01L29/66 ,  H01L21/84

Abstract: A transistor is fabricated by growing an epitaxial layer of semiconductor material on a semiconductor layer and forming an opening extending through the epitaxial layer at the gate location. This opening provides, from the epitaxial layer, a source epitaxial region on one side of the opening and a drain epitaxial region on an opposite side of the opening. The source epitaxial region and a first portion of the semiconductor layer underlying the source epitaxial region are annealed into a single crystal transistor source region. Additionally, the drain epitaxial region and a second portion of the semiconductor layer underlying the drain epitaxial region are annealed into a single crystal transistor drain region. A third portion of the semiconductor layer between the transistor source and drain regions forms a transistor channel region. A transistor gate electrode is then formed in the opening above the transistor channel region.

公开(公告)号：US09922993B2

公开(公告)日：2018-03-20

申请号：US15292465

申请日：2016-10-13

Applicant: STMicroelectronics, Inc.

Inventor： John Hongguang Zhang

IPC: H01L27/12 ,  H01L29/417 ,  H01L21/84 ,  H01L29/66 ,  H01L21/768 ,  H01L21/285

CPC classification number: H01L27/1211 ,  H01L21/28518 ,  H01L21/76897 ,  H01L21/845 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66628

Abstract: A transistor includes an active region supported by a substrate and having a source region, a channel region and a drain region. A gate stack extends over the channel region and a first sidewall surrounds the gate stack. A raised source region and a raised drain region are provided over the source and drain regions, respectively, of the active region adjacent the first sidewall. A second sidewall peripherally surrounds each of the raised source region and raised drain region. The second sidewall extends above a top surface of the raised source region and raised drain region to define regions laterally delimited by the first and second sidewalls. A conductive material fills the regions to form a source contact and a drain contact to the raised source region and raised drain region, respectively.

公开(公告)号：US09818930B2

公开(公告)日：2017-11-14

申请号：US14938432

申请日：2015-11-11

Applicant: STMicroelectronics, Inc.

Inventor： John Hongguang Zhang

IPC: H01L41/332 ,  B23P15/00 ,  C03C25/00 ,  C23F1/00 ,  H01L41/09

CPC classification number: H01L41/332 ,  H01L41/0973

Abstract: A support structure includes an internal cavity. An elastic membrane extends to divide the internal cavity into a first chamber and a second chamber. The elastic membrane includes a nanometric-sized pin hole extending there through to interconnect the first chamber to the second chamber. The elastic membrane is formed of a first electrode film and a second electrode film separated by a piezo insulating film. Electrical connection leads are provided to support application of a bias current to the first and second electrode films of the elastic membrane. In response to an applied bias current, the elastic membrane deforms by bending in a direction towards one of the first and second chambers so as to produce an increase in a diameter of the pin hole.

公开(公告)号：US20160365309A1

公开(公告)日：2016-12-15

申请号：US14734013

申请日：2015-06-09

Applicant: STMicroelectronics, Inc.

Inventor： John Hongguang Zhang

IPC: H01L23/528 ,  H01L21/768 ,  H01L29/66 ,  H01L29/78 ,  H01L23/535

CPC classification number: H01L29/66545 ,  H01L21/28088 ,  H01L21/768 ,  H01L21/76877 ,  H01L21/76885 ,  H01L21/76897 ,  H01L23/528 ,  H01L23/535 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/42384 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/785 ,  H01L29/78645 ,  H01L29/78696

Abstract: An integrated circuit includes a source-drain region, a channel region adjacent to the source-drain region, a gate structure extending over the channel region and a sidewall spacer on a side of the gate structure and which extends over the source-drain region. A dielectric layer is provided in contact with the sidewall spacer and having a top surface. The gate structure includes a gate electrode and a gate contact extending from the gate electrode as a projection to reach the top surface. The side surfaces of the gate electrode and a gate contact are aligned with each other. The gate dielectric layer for the transistor positioned between the gate electrode and the channel region extends between the gate electrode and the sidewall spacer and further extends between the gate contact and the sidewall spacer.

Abstract translation: 集成电路包括源极 - 漏极区域，与源极 - 漏极区域相邻的沟道区域，在沟道区域上延伸的栅极结构和在栅极结构侧面上的侧壁间隔物并且在源极 - 漏极区域上延伸。 提供与侧壁间隔物接触并具有顶表面的电介质层。 栅极结构包括栅极电极和从栅电极延伸的栅极接触，作为突起到达顶表面。 栅电极和栅极触点的侧表面彼此对准。 位于栅电极和沟道区之间的晶体管的栅极电介质层在栅电极和侧壁间隔物之间​​延伸，并且进一步在栅极接触件和侧壁间隔件之间延伸。

公开(公告)号：US09484535B1

公开(公告)日：2016-11-01

申请号：US14960712

申请日：2015-12-07

Applicant: STMicroelectronics, Inc.

Inventor： Qing Liu ,  John Hongguang Zhang

IPC: H01L21/4763 ,  H01L45/00 ,  H01L27/24

CPC classification number: H01L27/2436 ,  H01L23/528 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/145 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1616 ,  H01L45/1633 ,  H01L45/1691

Abstract: A resistive random access memory (RRAM) structure is formed on a supporting substrate and includes a first electrode and a second electrode. The first electrode is made of a silicided fin on the supporting substrate and a first metal liner layer covering the silicided fin. A layer of dielectric material having a configurable resistive property covers at least a portion of the first metal liner. The second electrode is made of a second metal liner layer covering the layer of dielectric material and a metal fill in contact with the second metal liner layer. A non-volatile memory cell includes the RRAM structure electrically connected between an access transistor and a bit line.

Abstract translation: 在支撑衬底上形成电阻随机存取存储器（RRAM）结构，并且包括第一电极和第二电极。 第一电极由支撑衬底上的硅化物翅片和覆盖硅化物翅片的第一金属衬垫层制成。 具有可配置电阻性能的电介质材料层覆盖第一金属衬垫的至少一部分。 第二电极由覆盖电介质材料层的第二金属衬垫层和与第二金属衬垫层接触的金属填充物制成。 非易失性存储单元包括电连接在存取晶体管和位线之间的RRAM结构。

公开(公告)号：US20160300857A1

公开(公告)日：2016-10-13

申请号：US14680392

申请日：2015-04-07

Applicant: STMicroelectronics, Inc.

Inventor： Qing Liu ,  John Hongguang Zhang ,  Walter Kleemeier

IPC: H01L27/12 ,  H01L29/417 ,  H01L27/092 ,  H01L21/324 ,  H01L21/306 ,  H01L29/08 ,  H01L21/84

CPC classification number: H01L27/1211 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/41783 ,  H01L29/66545

Abstract: A junctionless field effect transistor on an insulating layer of a substrate includes a fin made of semiconductor material doped with a dopant of a first conductivity type. A channel made of an epitaxial semiconductor material region doped with a dopant of a second conductivity type is in contact with a top surface of the fin. An insulated metal gate straddles the channel. A source connection is made to the epitaxial semiconductor material region on one side of said insulated metal gate, and a drain connection is made to the epitaxial semiconductor material region on an opposite side of said insulated metal gate. The epitaxial channel may further be grown from and be in contact with opposed side surfaces of the fin.

Abstract translation: 在基板的绝缘层上的无连接场效应晶体管包括由掺杂有第一导电类型的掺杂剂的半导体材料制成的鳍。 由掺杂有第二导电类型的掺杂剂的外延半导体材料区域形成的沟道与鳍片的顶表面接触。 绝缘金属门横跨通道。 源极连接到所述绝缘金属栅极的一侧上的外延半导体材料区域，并且在所述绝缘金属栅极的相对侧上的外延半导体材料区域进行漏极连接。 外延沟道还可以从翅片的相对的侧表面生长并与其接触。

公开(公告)号：US20160293602A1

公开(公告)日：2016-10-06

申请号：US14677404

申请日：2015-04-02

Applicant: STMicroelectronics, Inc.

Inventor： Qing Liu ,  John Hongguang Zhang

IPC: H01L27/098 ,  H01L29/808 ,  H01L21/283 ,  H01L29/417 ,  H01L29/10 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/66893 ,  H01L21/283 ,  H01L27/098 ,  H01L29/0657 ,  H01L29/1058 ,  H01L29/1066 ,  H01L29/165 ,  H01L29/41741 ,  H01L29/41791 ,  H01L29/66909 ,  H01L29/7832 ,  H01L29/8083

Abstract: A vertical junction field effect transistor (JFET) is supported by a semiconductor substrate that includes a source region within the semiconductor substrate doped with a first conductivity-type dopant. A fin of semiconductor material doped with the first conductivity-type dopant has a first end in contact with the source region and further includes a second end and sidewalls between the first and second ends. A drain region is formed of first epitaxial material grown from the second end of the fin and doped with the first conductivity-type dopant. A gate structure is formed of second epitaxial material grown from the sidewalls of the fin and doped with a second conductivity-type dopant.

Abstract translation: 垂直结型场效应晶体管（JFET）由包括掺杂有第一导电型掺杂剂的半导体衬底内的源极区域的半导体衬底支撑。 掺杂有第一导电型掺杂剂的半导体材料的鳍具有与源极区域接触的第一端，并且还包括第二端和第二端之间的侧壁。 漏极区域由从鳍片的第二端生长并掺杂有第一导电型掺杂剂的第一外延材料形成。 栅极结构由从鳍的侧壁生长并掺杂有第二导电型掺杂剂的第二外延材料形成。