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    Method for writing in an EEPROM-type memory including a memory cell refresh
    11.
    发明授权
    Method for writing in an EEPROM-type memory including a memory cell refresh 有权
    用于写入包括存储单元刷新的EEPROM型存储器的方法

    公开(公告)号：US09099186B2

    公开(公告)日：2015-08-04

    申请号：US14293870

    申请日：2014-06-02

    Applicant: STMicroelectronics (Rousset) SAS

    Inventor： Francois Tailliet

    IPC: G11C16/04 ,  G11C16/02 ,  G11C16/14 ,  G11C16/10 ,  G11C16/06 ,  G11C16/24 ,  G11C16/08 ,  G11C16/16 ,  G11C11/56

    CPC classification number: G11C16/14 ,  G11C11/5628 ,  G11C16/0433 ,  G11C16/0483 ,  G11C16/06 ,  G11C16/08 ,  G11C16/10 ,  G11C16/16

    Abstract: The present disclosure relates to a method for writing in an EEPROM memory, the method comprising steps of: storing the bits of a word to be written in first memory units, erasing a word to be modified, formed by first memory cells connected to a word line and first bit lines, reading bits stored in the memory cells of a word line WL , in a first read mode and storing the bits read in second memory units, reading in a second read mode the bits stored in the memory cells of the word line, and programming each memory cell of the word line connected to a memory unit storing a bit in the programmed state of the word to be written, of an erased word or of a word comprising a bit having different states in the first and second read modes.

    Abstract translation: 本发明涉及一种在EEPROM存储器中写入的方法，该方法包括以下步骤：将要写入的字的位存储在第一存储单元中，擦除要连接到字的第一存储器单元形成的要修改的字 行和第一位线，以第一读取模式读取存储在字线WL的存储单元中的位，并存储读入第二存储器单元的位，读取第二读取模式存储在存储器单元中的位 并且将连接到存储单元的字线的每个存储器单元编程为存储要写入的字的编程状态的位的擦除字或包括在第一个中包含不同状态的位的字的字 和第二读取模式。

    METHOD FOR BLOCK-ERASING A PAGE-ERASABLE EEPROM-TYPE MEMORY
    12.
    发明申请
    METHOD FOR BLOCK-ERASING A PAGE-ERASABLE EEPROM-TYPE MEMORY 有权
    用于块擦除可擦除EEPROM类型存储器的方法

    公开(公告)号：US20140362640A1

    公开(公告)日：2014-12-11

    申请号：US14293860

    申请日：2014-06-02

    Applicant: STMicroelectronics (Rousset) SAS

    Inventor： Francois Tailliet

    IPC: G11C16/14

    CPC classification number: G11C16/14 ,  G11C11/5635 ,  G11C16/0483 ,  G11C16/16

    Abstract: A method for erasing a page-erasable EEPROM-type memory includes: the memory receiving a command associated with a set of addresses of pages of the memory to be erased, each page comprising several memory cell groups each forming a word, for each address of the set of addresses, selecting a word line corresponding to a page of the memory, and triggering the simultaneous erasing of all the selected word lines.

    Abstract translation: 擦除可擦除可擦除EEPROM型存储器的方法包括：存储器接收与要擦除的存储器的页面的一组地址相关联的命令，每个页面包括几个存储单元组，每个存储单元组形成一个单词，每个地址为 所述地址集合，选择与所述存储器的页面对应的字线，并且触发所有所选字线的同时擦除。

    Method for Managing the Operation of a Circuit Connected to a Two-Wire Bus
    13.
    发明申请
    Method for Managing the Operation of a Circuit Connected to a Two-Wire Bus 有权
    管理连接到两线总线的电路的操作方法

    公开(公告)号：US20140095750A1

    公开(公告)日：2014-04-03

    申请号：US14042344

    申请日：2013-09-30

    Applicant: STMicroelectronics Rousset) SAS

    Inventor： Francois Tailliet

    IPC: G06F13/42

    CPC classification number: G06F13/4282 ,  G06F13/4077

    Abstract: A method is provided for managing the operation of a circuit operating in a slave mode. The circuit is connected to a bus having at least two of wires and a priority logic level. The slave circuit imposes the priority logic level on a first wire of the bus. While imposing, the slave circuit detects a possible conflict on the first wire resulting from a forcing, external to the slave circuit, of the first wire to another logic level. Upon detecting a conflict, the slave circuit is placed in a state stopping the sending by the circuit of any data over the bus while leaving the circuit listening to the bus.

    Abstract translation: 提供了一种用于管理在从模式下操作的电路的操作的方法。 电路连接到具有至少两根导线和优先级逻辑电平的总线。 从电路在总线的第一根线上施加优先级逻辑电平。 在施加时，从电路检测到第一线上的强制（从属电路外部）将第一导线的第一导线的可能冲突与第一导线的另一逻辑电平相冲突。 在检测到冲突时，从电路处于停止通过总线发送任何数据的状态，同时让电路监听总线。

    Integrated device for protection from electrostatic discharges
    15.
    发明授权
    Integrated device for protection from electrostatic discharges 有权

    公开(公告)号：US11244941B2

    公开(公告)日：2022-02-08

    申请号：US16877935

    申请日：2020-05-19

    Applicant: STMicroelectronics (Rousset) SAS

    Inventor： Francois Tailliet

    IPC: H01L27/02 ,  H01L23/50

    Abstract: A first power supply rail is provided as a power supply tree configured with couplings to distribute a supply voltage to active elements of the circuit. A second power supply rail is provided as an electrostatic discharge channel and is not configured with distribution tree couplings to active elements of the circuit. A first electrostatic discharge circuit is directly electrically connected between one end of the second power supply rail and a ground rail. A second electrostatic discharge circuit is directly electrically connected between an interconnect node and the ground rail. The interconnect node electrically interconnects another end of the second power supply rail to the first power supply rail at the second electrostatic discharge circuit.

    MOS transistors in parallel
    16.
    发明授权
    MOS transistors in parallel 有权

    公开(公告)号：US10903209B2

    公开(公告)日：2021-01-26

    申请号：US16053304

    申请日：2018-08-02

    Applicant: STMicroelectronics (Rousset) SAS

    Inventor： Francois Tailliet

    IPC: H01L21/762 ,  H01L21/8234 ,  H01L29/10 ,  H01L27/088 ,  H01L29/06 ,  H01L29/78

    Abstract: An electronic chip is provided that includes a plurality of first transistors electrically coupled to one another in parallel. A plurality of first isolating trenches is included in the electronic chip, and the first transistors are separated from one another by the first isolating trenches. Each of the first isolation trenches has a depth and a maximum width, and the depth depends on, or is a function of, the maximum width.

    SECURE MEMORY WHICH REDUCES DEGRADATION OF DATA
    18.
    发明申请
    SECURE MEMORY WHICH REDUCES DEGRADATION OF DATA 审中-公开
    减少数据降级的安全存储器

    公开(公告)号：US20150109861A1

    公开(公告)日：2015-04-23

    申请号：US14584165

    申请日：2014-12-29

    Applicant: STMICROELECTRONICS (ROUSSET) SAS

    Inventor： Francois Tailliet

    IPC: G11C16/10 ,  G11C16/34 ,  G11C16/26

    CPC classification number: G11C16/10 ,  G06F11/167 ,  G06F11/20 ,  G11C16/26 ,  G11C16/3404 ,  G11C16/3495 ,  G11C29/74

    Abstract: A method for managing a non-volatile memory may include a first phase of writing data to a first bank of a memory plane of the non-volatile memory, and then a second phase of writing the same data to a second bank of the same memory plane of the non-volatile memory in the case of success of the first writing phase.

    Abstract translation: 用于管理非易失性存储器的方法可以包括将数据写入非易失性存储器的存储器平面的第一组的第一阶段，然后将相同数据写入同一存储器的第二组的第二阶段 在第一写入阶段成功的情况下，非易失性存储器的平面。

    LOW PASS FILTER WITH AN INCREASED DELAY
    19.
    发明申请
    LOW PASS FILTER WITH AN INCREASED DELAY 有权
    低通滤波器具有增加的延迟

    公开(公告)号：US20130278330A1

    公开(公告)日：2013-10-24

    申请号：US13868866

    申请日：2013-04-23

    Applicant: STMICROELECTRONICS (ROUSSET) SAS

    Inventor： Francois Tailliet ,  Marc Battista

    IPC: H03H11/04

    CPC classification number: H03H11/04 ,  H03K5/1252 ,  H03K5/13 ,  H03K2005/00156

    Abstract: A low pass filter comprises a filter input node configured to receive a first logic signal, a filter output node configured to supply a second logic signal, a resistive element comprising a first terminal coupled to the input node and a second terminal coupled to the output node, and a capacitive element comprising a first terminal coupled to the output node and a second terminal. The filter further comprises an inverting gate having a first terminal coupled to the input node and a second terminal coupled to the second terminal of the capacitive element.

    Abstract translation: 低通滤波器包括被配置为接收第一逻辑信号的滤波器输入节点，被配置为提供第二逻辑信号的滤波器输出节点，包括耦合到输入节点的第一终端的电阻元件和耦合到输出节点的第二终端 以及电容元件，包括耦合到所述输出节点的第一端子和第二端子。 滤波器还包括反相门，其具有耦合到输入节点的第一端子和耦合到电容元件的第二端子的第二端子。

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