公开(公告)号：US09940997B2

公开(公告)日：2018-04-10

申请号：US15447853

申请日：2017-03-02

Applicant: STMicroelectronics International N.V.

Inventor： Ashish Kumar ,  Vinay Kumar ,  Kedar Janardan Dhori

IPC: G11C11/00 ,  G11C11/419 ,  G11C11/418 ,  G11C5/14

CPC classification number: G11C11/419 ,  G11C5/063 ,  G11C5/145 ,  G11C5/147 ,  G11C11/418

Abstract: Read stability of a memory is enhanced in low voltage operation mode by selectively boosting a cell supply voltage for a row of memory cells. The boosted voltage results from a capacitive coupling to the word line in that row. The capacitive coupling is implemented by running the metal line of the power supply line for the cell supply voltage and the metal line for the word line adjacent to each other in a common metallization level. The selective voltage boost is controlled in response to operation of a modified memory cell exhibiting a deteriorated write margin. An output of the modified memory cell is compared to a threshold to generate a signal for controlling the selective voltage boost. Word line under-voltage circuitry is further provided to control application of an under-voltage to the word line.

公开(公告)号：US09866233B1

公开(公告)日：2018-01-09

申请号：US15631330

申请日：2017-06-23

Applicant: STMicroelectronics International N.V.

Inventor： Ashish Kumar ,  Chandrajit Debnath ,  Pratap Narayan Singh

IPC: H03M1/12 ,  H03M1/46

CPC classification number: H03M1/466 ,  H03M1/0863 ,  H03M1/1009 ,  H03M1/124 ,  H03M1/1245 ,  H03M1/164 ,  H03M1/38 ,  H03M1/44

Abstract: An embodiment circuit includes a first reference source configured to provide a first reference signal to an analog-to-digital convertor (ADC). The circuit also includes a filter coupled to an output of the first reference source and configured to filter the first reference signal to produce a filtered first reference signal. The circuit further includes a second reference source coupled to an output of the filter. The second reference source is configured to provide a second reference signal to the ADC, and the second reference signal is generated based on the filtered first reference signal.

公开(公告)号：US20170316820A1

公开(公告)日：2017-11-02

申请号：US15447853

申请日：2017-03-02

Applicant: STMicroelectronics International N.V.

Inventor： Ashish Kumar ,  Vinay Kumar ,  Dhori Kedar Janardan

IPC: G11C11/419 ,  G11C11/418

CPC classification number: G11C11/419 ,  G11C5/063 ,  G11C5/145 ,  G11C5/147 ,  G11C11/418

Abstract: Read stability of a memory is enhanced in low voltage operation mode by selectively boosting a cell supply voltage for a row of memory cells. The boosted voltage results from a capacitive coupling to the word line in that row. The capacitive coupling is implemented by running the metal line of the power supply line for the cell supply voltage and the metal line for the word line adjacent to each other in a common metallization level. The selective voltage boost is controlled in response to operation of a modified memory cell exhibiting a deteriorated write margin. An output of the modified memory cell is compared to a threshold to generate a signal for controlling the selective voltage boost. Word line under-voltage circuitry is further provided to control application of an under-voltage to the word line.

公开(公告)号：US20170301396A1

公开(公告)日：2017-10-19

申请号：US15132680

申请日：2016-04-19

Applicant: STMicroelectronics International N.V.

Inventor： Kedar Janardan Dhori ,  Ashish Kumar ,  Hitesh Chawla ,  Praveen Kumar Verma

IPC: G11C11/419

CPC classification number: G11C11/419 ,  G11C8/08 ,  G11C11/418

Abstract: A memory circuit includes a wordline, memory cells connected to the wordline and a wordline driver circuit including a p-channel pull-up transistor. The memory circuit further includes a read assist circuit including an n-channel pull-down transistor having a source-drain path connected between the wordline and a ground node and an n-channel diode-connected transistor having a source-drain path connected between a positive supply node and a gate terminal of the n-channel pull-down transistor. The n-channel diode-connected transistor is configured to apply a biasing voltage to the gate terminal of the n-channel pull-down transistor that is a relatively lower voltage for relatively lower temperatures and a relatively higher voltage for relatively higher temperatures.

公开(公告)号：US09412424B2

公开(公告)日：2016-08-09

申请号：US14107982

申请日：2013-12-16

Applicant: STMicroelectronics International N.V.

Inventor： Ashish Kumar ,  Manish Umedlal Patel

IPC: G11C7/00 ,  G11C7/06 ,  G11C8/12

CPC classification number: G11C7/00 ,  G11C7/065 ,  G11C8/12 ,  G11C2207/005

Abstract: A device and a method for a sense circuit have been disclosed. In an implementation, the sense circuit includes a sense amplifier and at least one decoupling device. The decoupling device is coupled to the sense amplifier through at least one reference line. The sense amplifier reads a data value and the decoupling device decouples the sense amplifier from a power supply during a read operation.

Abstract translation: 已经公开了一种用于感测电路的装置和方法。 在实现中，感测电路包括读出放大器和至少一个解耦装置。 解耦器件通过至少一个参考线耦合到读出放大器。 读出放大器读取数据值，去耦器件在读取操作期间将读出放大器与电源解耦。

公开(公告)号：US10171100B2

公开(公告)日：2019-01-01

申请号：US16031753

申请日：2018-07-10

Applicant: STMicroelectronics International N.V.

Inventor： Ashish Kumar ,  Chandrajit Debnath ,  Pratap Narayan Singh

IPC: H03M1/12 ,  H03M1/46 ,  H03M1/08 ,  H03M1/44 ,  H03M1/16 ,  H03M1/38 ,  H03M1/10

Abstract: An embodiment circuit includes a first reference source configured to provide a first reference signal to an analog-to-digital convertor (ADC). The circuit also includes a filter coupled to an output of the first reference source and configured to filter the first reference signal to produce a filtered first reference signal. The circuit further includes a second reference source coupled to an output of the filter. The second reference source is configured to provide a second reference signal to the ADC, and the second reference signal is generated based on the filtered first reference signal.

公开(公告)号：US09685209B1

公开(公告)日：2017-06-20

申请号：US15132388

申请日：2016-04-19

Applicant: STMicroelectronics International N.V.

Inventor： Kedar Janardan Dhori ,  Vinay Kumar ,  Ashish Kumar

IPC: G11C7/00 ,  G11C7/12 ,  G11C7/14 ,  G11C7/06

CPC classification number: G11C7/12 ,  G11C7/062 ,  G11C7/08 ,  G11C7/14 ,  G11C7/227 ,  G11C11/419

Abstract: A sense amplifier enable signal generating circuit includes an input coupled to a dummy bit line of a memory. A voltage comparator circuit compares a voltage on the dummy bit line to a threshold voltage and generates an output signal when the voltage falls below that threshold voltage. A multi-bit counter circuit counts a count value in response to the output signal. A pull-up circuit pulls up the voltage on the dummy bit line in response to the output signal. A count comparator circuit compares the count value to a count threshold and generates a sense amplifier enable signal when the count value equals the count threshold.