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公开(公告)号：US20180248544A1
公开(公告)日：2018-08-30
申请号：US15690963
申请日：2017-08-30
Applicant: STMicroelectronics S.r.l.
Inventor： Davide Ugo Ghisu , Sandro Rossi , Andrea Gambero
IPC: H03K17/567 , H03K5/08 , A61B8/00
CPC classification number: H03K17/567 , A61B8/54 , B06B1/0215 , B06B2201/77 , H03K5/023 , H03K5/08
Abstract: A driver circuit for driving, for example, ultrasonic transducers in medical equipment, such as ultrasound scanning equipment. The driver circuit includes first inputs receptive of a pulsed signal, second inputs receptive of an analog signal, an output for applying a pulsed drive signal or an analog drive signal to a load. A pair of output transistors of complementary polarities are positioned with their current paths in series between opposing supply lines with a connection point intermediate between the transistors of the pair of transistors. The connection point between output transistors is coupled to the output of the circuit. The control terminals of the output transistors, which are coupled together, may be coupled to the first inputs with the driver functioning as a pulser, or else coupled to the second inputs with the driver functioning as a linear driver.
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公开(公告)号：US09966944B2
公开(公告)日：2018-05-08
申请号：US15216271
申请日：2016-07-21
Applicant: STMicroelectronics S.R.L.
Inventor： Sandro Rossi , Valeria Bottarel
IPC: H03K3/00 , H03K17/687 , H03K19/0175
CPC classification number: H03K17/687 , H03K3/3565 , H03K17/04123 , H03K17/063 , H03K17/6872 , H03K19/017509 , H03K19/018521 , H03K2217/0036 , H03K2217/0045
Abstract: A gate driver circuit for a half bridge or full bridge output driver stage having a high side branch connected to one or more high side transistors and a low side branch connected to one or more low side transistors. A high side gate driver and a low side gate driver receive input signals at a low voltage level and output signals at a high voltage level as gate driving signals for the high side transistors and low side transistors. Each of the high side and the low side branches of the gate driver includes a set-reset latch having a signal output that is fed as a gate signal to the corresponding transistor of the half bridge or full bridge driver. A differential capacitive level shifter circuit receives the input signals at a low voltage level and outputs high voltage signals to drive the set and reset inputs of the set-reset latch.
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公开(公告)号：US09772645B2
公开(公告)日：2017-09-26
申请号：US15076211
申请日：2016-03-21
Applicant: STMicroelectronics S.r.l.
Inventor： Sandro Rossi , Davide Ugo Ghisu , Fabio Quaglia , Antonio Davide Leone
CPC classification number: G05F3/02 , B06B1/0215 , H03K4/94 , H03K17/162
Abstract: A transmission channel transmits high-voltage pulses and receives echos of the high-voltage pulses. The transmission channel includes a current generator circuit, which generates current-integrator drive currents. The control circuitry generates one or more control signals to control generation of current-integrator drive currents by the current generator circuit during transducer-driving periods. A current integrator integrates current-integrator drive currents generated by current generator circuit to generate transducer drive signals.
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公开(公告)号：US20160332196A1
公开(公告)日：2016-11-17
申请号：US15220208
申请日：2016-07-26
Applicant: STMicroelectronics S.r.l.
Inventor： Davide Ugo Ghisu , Sandro Rossi , Dario Bianchi
IPC: B06B1/02 , H03K17/687
Abstract: A transmission channel transmits high-voltage pulses in a transmission phase and receives echoes of the high-voltage pulses in a receiving phase. The transmission channel includes a buffer with anti-memory circuitry to couple drain conduction terminals of buffer transistors of a high-side of a buffer of the transmission channel to a low-side reference voltage of a low-side of the buffer and couple drain conduction terminals of buffer transistors of the low-side of the buffer to a high-side reference voltage of the high-side of the buffer during the clamping phase.
Abstract translation: 传输通道在传输阶段传输高电压脉冲，并在接收阶段接收高电压脉冲的回波。 传输通道包括具有防存储器电路的缓冲器，用于将传输通道的缓冲器的高侧的缓冲晶体管的漏极导通端子耦合到缓冲器的低侧的低侧参考电压并耦合漏极导通 缓冲器的低侧的缓冲晶体管的端子在钳位阶段期间到缓冲器的高侧的高侧参考电压。
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公开(公告)号：US10734954B2
公开(公告)日：2020-08-04
申请号：US15691298
申请日：2017-08-30
Applicant: STMicroelectronics S.r.l.
Inventor： Andrea Gambero , Davide Ugo Ghisu , Sandro Rossi
Abstract: An operational amplifier including an input stage coupled to an input terminal, an output stage coupled to an output terminal, and a gain node between the input stage and the output stage. A bias current source is couplable to the input stage to supply a bias current thereto and a current mirror circuit mirrors the bias current toward the gain node and the output stage. A switch circuit includes a switch activatable to bring the gain node to a pre-bias voltage and a switch coupled to the output stage and switchable between a first state and a second state in which the output stage is active and non-active, respectively—. A further switch circuit is coupled to the output terminal and switchable between a first state and a second state in which the output stage is coupled to the output terminal and to a reference level, respectively.
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Patent Agency Ranking
公开(公告)号：US10441972B2
公开(公告)日：2019-10-15
申请号：US15220208
申请日：2016-07-26
Applicant: STMicroelectronics S.r.l.
Inventor： Davide Ugo Ghisu , Sandro Rossi , Dario Bianchi
IPC: G05F3/02 , B06B1/02 , H03K19/0185 , H03K17/687 , H03K3/356 , H03K17/082 , A61B8/00
Abstract: A transmission channel transmits high-voltage pulses in a transmission phase and receives echoes of the high-voltage pulses in a receiving phase. The transmission channel includes a buffer with anti-memory circuitry to couple drain conduction terminals of buffer transistors of a high-side of a buffer of the transmission channel to a low-side reference voltage of a low-side of the buffer and couple drain conduction terminals of buffer transistors of the low-side of the buffer to a high-side reference voltage of the high-side of the buffer during the clamping phase.
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公开(公告)号：US20180248522A1
公开(公告)日：2018-08-30
申请号：US15691298
申请日：2017-08-30
Applicant: STMicroelectronics S.r.l.
Inventor： Andrea Gambero , Davide Ugo Ghisu , Sandro Rossi
CPC classification number: H03F1/305 , H03F1/307 , H03F3/187 , H03F3/217 , H03F3/302 , H03F3/45475 , H03F3/72 , H03F2200/03 , H03F2200/297 , H03F2200/516 , H03F2203/30099 , H03F2203/30132 , H04R3/00
Abstract: An operational amplifier including an input stage coupled to an input terminal, an output stage coupled to an output terminal, and a gain node between the input stage and the output stage. A bias current source is couplable to the input stage to supply a bias current thereto and a current mirror circuit mirrors the bias current toward the gain node and the output stage. A switch circuit includes a switch activatable to bring the gain node to a pre-bias voltage and a switch coupled to the output stage and switchable between a first state and a second state in which the output stage is active and non-active, respectively—. A further switch circuit is coupled to the output terminal and switchable between a first state and a second state in which the output stage is coupled to the output terminal and to a reference level, respectively.
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公开(公告)号：US09886940B2
公开(公告)日：2018-02-06
申请号：US14518894
申请日：2014-10-20
Applicant: STMicroelectronics S.r.l.
Inventor： Matteo Albertini , Sandro Rossi
IPC: H03K5/08 , G10K11/18 , H03K3/355 , H03K5/125 , H03K19/0175 , H03K19/0185 , H03K5/003 , B06B1/02
CPC classification number: G10K11/18 , B06B1/0215 , B06B2201/76 , H03K3/355 , H03K5/003 , H03K5/125 , H03K19/017509 , H03K19/018521
Abstract: A device voltage shifter includes a first voltage reference node, a second voltage reference node, an output node and a clamp node. A first high-voltage switching transistor of the voltage shifter has a first conduction terminal coupled to the first voltage reference node and a second conduction terminal coupled to the clamp node. A second high-voltage switching transistor of the voltage shifter has a first conduction terminal coupled to the clamp node and a second conduction terminal coupled to the second voltage reference node. A third high-voltage switching transistor of the voltage shifter has a first conduction terminal coupled to the first voltage reference node, a control terminal coupled to the clamp node, and a second conduction terminal coupled to the output node. A voltage regulator of the voltage shifter is coupled between the output node and the clamp node.
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公开(公告)号：US20170257092A1
公开(公告)日：2017-09-07
申请号：US15216271
申请日：2016-07-21
Applicant: STMicroelectronics S.R.L.
Inventor： Sandro Rossi , Valeria Bottarel
IPC: H03K17/687 , H03K19/0175
CPC classification number: H03K17/687 , H03K3/3565 , H03K17/04123 , H03K17/063 , H03K17/6872 , H03K19/017509 , H03K19/018521 , H03K2217/0036 , H03K2217/0045
Abstract: A gate driver circuit for a half bridge or full bridge output driver stage having a high side branch connected to one or more high side transistors and a low side branch connected to one or more low side transistors. A high side gate driver and a low side gate driver receive input signals at a low voltage level and output signals at a high voltage level as gate driving signals for the high side transistors and low side transistors. Each of the high side and the low side branches of the gate driver includes a set-reset latch having a signal output that is fed as a gate signal to the corresponding transistor of the half bridge or full bridge driver. A differential capacitive level shifter circuit receives the input signals at a low voltage level and outputs high voltage signals to drive the set and reset inputs of the set-reset latch.
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公开(公告)号：US09442507B2
公开(公告)日：2016-09-13
申请号：US14573438
申请日：2014-12-17
Applicant: STMicroelectronics S.r.l.
Inventor： Davide Ugo Ghisu , Sandro Rossi , Dario Bianchi
IPC: H03L5/00 , G05F3/02 , H03K19/0185 , H03K17/687 , H03K3/356
CPC classification number: B06B1/0215 , A61B8/4483 , G05F3/02 , H03K3/356182 , H03K17/0822 , H03K17/687 , H03K19/018521 , H03K2217/0063
Abstract: A transmission channel transmits high-voltage pulses and receives echos of the high-voltage pulses. The transmission channel includes a buffer with anti-memory circuitry to couple drains of the buffer transistors to voltage reference terminals during a clamping phase.
Abstract translation: 传输通道传输高电压脉冲并接收高电压脉冲的回波。 传输通道包括具有防存储器电路的缓冲器，以在夹持阶段将缓冲晶体管的漏极耦合到电压参考端子。
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