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11.发明授权公开(公告)号：US11289158B2
公开(公告)日：2022-03-29
申请号：US17123518
申请日：2020-12-16
Applicant: STMicroelectronics S.r.l.
IPC: G11C13/00
Abstract: An embodiment non-volatile memory device includes an array of memory cells, coupled to word lines, and a row decoder including a pull-down stage and a pull-up stage, which includes, for each word line: a corresponding control circuit, which generates a corresponding control signal; and a corresponding pull-up switch circuit, which is controlled via the control signal so as to couple/decouple the word line to/from the supply. The control circuit includes: a current mirror, which injects a current into an internal node; and a series circuit, which couples/decouples the corresponding internal node to/from ground, on the basis of selection/deselection of the corresponding word line so as to cause a decrease/increase in a voltage on the corresponding internal node. Each control signal is a function of the voltage on the corresponding internal node.
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12.发明申请公开(公告)号：US20210233582A1
公开(公告)日：2021-07-29
申请号：US17159381
申请日：2021-01-27
Applicant: STMicroelectronics S.r.l.
IPC: G11C13/00
Abstract: An embodiment voltage generation circuit, for a memory having a memory array with a plurality of memory cells coupled to respective wordlines and local bit-lines, each having a storage element and selector element, a bipolar transistor being coupled to the storage element for selective flow of a cell current during reading or verifying operations, and a base terminal of the selector element being coupled to a respective wordline; associated to each bit-line is a biasing transistor having a control terminal, and the circuit generates a cascode voltage for this control terminal; a driver stage is coupled to one end of each wordline. The circuit generates the cascode voltage based on a reference voltage, which is a function of the emulation of a voltage drop on the driver stage, on the wordline, and on the memory cell as a result of a current associated to the corresponding selector element.
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公开(公告)号：US10255973B2
公开(公告)日：2019-04-09
申请号：US15797732
申请日：2017-10-30
Applicant: STMicroelectronics S.r.l.
Inventor： Davide Manfre , Cesare Torti , Fabio Enrico Carlo Disegni
Abstract: An embodiment memory device includes a memory array having a plurality of bit lines, a low-voltage connection path configured to connect, in an operational phase of the device, an access terminal to a selected local bit line of the plurality of bit lines, and a high-voltage connection path configured to connect, in the operational phase of the device, the access terminal to the selected local bit line, in parallel with the low-voltage connection path.
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14.发明申请公开(公告)号：US20180122470A1
公开(公告)日：2018-05-03
申请号：US15598962
申请日：2017-05-18
Applicant: STMicroelectronics S.r.l.
IPC: G11C13/00
CPC classification number: G11C13/0069 , G11C13/0004 , G11C13/0023 , G11C13/004 , G11C13/0097 , G11C2013/0045 , G11C2013/0078 , G11C2213/79 , G11C2213/82
Abstract: A non-volatile memory includes a number of bit lines, a number of source lines, and a number of memory cells of a non-volatile type. Each memory cell is coupled between a respective bit line and a respective source line. One or more discharge lines are coupled to a reference-voltage terminal. A number of controlled switches are coupled between a respective source line and a respective discharge line, which can be selectively driven for connecting the respective source line to the respective discharge line so as to form a conductive path between the respective source line and the reference-voltage terminal.
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15.发明授权公开(公告)号：US11322201B2
公开(公告)日：2022-05-03
申请号：US17159381
申请日：2021-01-27
Applicant: STMicroelectronics S.r.l.
IPC: G11C13/00
Abstract: An embodiment voltage generation circuit, for a memory having a memory array with a plurality of memory cells coupled to respective wordlines and local bit-lines, each having a storage element and selector element, a bipolar transistor being coupled to the storage element for selective flow of a cell current during reading or verifying operations, and a base terminal of the selector element being coupled to a respective wordline; associated to each bit-line is a biasing transistor having a control terminal, and the circuit generates a cascode voltage for this control terminal; a driver stage is coupled to one end of each wordline. The circuit generates the cascode voltage based on a reference voltage, which is a function of the emulation of a voltage drop on the driver stage, on the wordline, and on the memory cell as a result of a current associated to the corresponding selector element.
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Patent Agency Ranking
公开(公告)号：US20210366554A1
公开(公告)日：2021-11-25
申请号：US17306266
申请日：2021-05-03
Inventor： Fabio Enrico Carlo Disegni , Laura Capecchi , Marcella Carissimi , Vikas Rana , Cesare Torti
Abstract: An embodiment non-volatile memory device includes an array of memory cells in rows and columns; a plurality of local bitlines, the memory cells of each column being coupled to a corresponding local bitline; a plurality of main bitlines, each main bitline being coupleable to a corresponding subset of local bitlines; a plurality of program driver circuits, each having a corresponding output node and injecting a programming current in the corresponding output node, each output node coupleable to a corresponding subset of main bitlines. Each program driver circuit further includes a corresponding limiter circuit that is electrically coupled, for each main bitline of the corresponding subset, to a corresponding sense node whose voltage depends, during writing, on the voltage on the corresponding main bitline. Each limiter circuit turns off the corresponding programming current, in case the voltage on any of the corresponding sense nodes overcomes a reference voltage.
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17.发明申请公开(公告)号：US20210166745A1
公开(公告)日：2021-06-03
申请号：US17088060
申请日：2020-11-03
Applicant: STMicroelectronics S.r.l.
Inventor： Fabio Enrico Carlo Disegni , Maurizio Francesco Perroni , Cesare Torti , Guiseppe Scardino
Abstract: A non-volatile memory device including an array of memory cells coupled to word lines and a row decoder, which includes a first and a second pull-down stage, which are arranged on opposite sides of the array, and include, respectively, for each word line, a corresponding first pull-down switching circuit and a corresponding second pull-down switching circuit, which are coupled to a first point and a second point, respectively, of the first word line. The row decoder moreover comprises a pull-up stage, which includes, for each word line, a corresponding pull-up switching circuit, which can be electronically controlled in order to: couple the first point to a supply node in the step of deselection of the word line; and decouple the first point from the supply node in the step of selection of the word line.
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公开(公告)号：US10861543B2
公开(公告)日：2020-12-08
申请号：US16804698
申请日：2020-02-28
Applicant: STMicroelectronics S.r.l.
Inventor： Fabio Enrico Carlo Disegni , Cesare Torti , Davide Manfré
Abstract: In one embodiment, a memory device includes a first sense amplifier, a second sense amplifier, a first lower switch arranged between a first lower main bit line and a first input of the first sense amplifier, a second lower switch arranged between the first lower main bit line and a first input of the second sense amplifier, a first upper switch arranged between a first upper main bit line and the first input of the first sense amplifier, a second upper switch arranged between the first upper main bit line and the first input of the second sense amplifier, a third lower switch arranged between a second lower main bit line to a second input of the first sense amplifier, and a third upper switch arranged between a second upper main bit line to a second input of the second sense amplifier.
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公开(公告)号：US10658032B2
公开(公告)日：2020-05-19
申请号：US16155659
申请日：2018-10-09
Applicant: STMicroelectronics S.r.l.
Inventor： Cesare Torti , Fabio Enrico Carlo Disegni , Davide Manfré , Massimo Fidone
Abstract: A memory device includes an array of phase-change memory cells and a word line. The memory device includes a control circuit, a first pull-up MOSFET and a second pull-up MOSFET connected in series between a first power-supply node set at a first supply voltage and the word line, a first pull-down MOSFET and a second pull-down MOSFET connected in series between the word line and a second power-supply node set at a reference potential, and a biasing MOSFET connected between the word line and a third power-supply node set at a second supply voltage higher than the first supply voltage. The first and second pull-up MOSFETs and the first and second pull-down MOSFETs have breakdown voltages lower than the breakdown voltage of the biasing MOSFET.
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公开(公告)号：US10600479B2
公开(公告)日：2020-03-24
申请号：US16227438
申请日：2018-12-20
Applicant: STMicroelectronics S.r.l.
Inventor： Fabio Enrico Carlo Disegni , Cesare Torti , Davide Manfré
Abstract: A memory device including a first memory sector and a second memory sector, each of which includes a respective plurality of local bit lines, which may be selectively coupled to a plurality of main bit lines. The memory device further includes a first amplifier and a second amplifier, and a routing circuit, arranged between the main bit lines and the first and second amplifiers. The routing circuit includes: a first lower switch, arranged between a first lower main bit line and a first input of the first amplifier; a second lower switch, arranged between the first lower main bit line and a first input of the second amplifier; a first upper switch, arranged between a first upper main bit line and the first input of the first amplifier; and a second upper switch, arranged between the first upper main bit line and the first input of the second amplifier. The second inputs of the first and second amplifiers are coupled to a second lower main bit line and to a second upper main bit line, respectively.
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