公开(公告)号：US06693042B1

公开(公告)日：2004-02-17

申请号：US09752539

申请日：2000-12-28

Applicant: Mehran G. Sedigh ,  Jianmin Qiao ,  Sam Geha

Inventor： Mehran G. Sedigh ,  Jianmin Qiao ,  Sam Geha

IPC: H01L21302

CPC classification number: H01L21/76802 ,  H01L21/31116

Abstract: A method for etching a dielectric layer formed upon a barrier layer with an etch chemistry including CxHyFz, in which x≧2, y≧2, and z≧2 is provided. Such an etch chemistry may be selective to the barrier layer. For example, the etch chemistry may have a dielectric layer:barrier layer selectivity of at least approximately 20:1, but may range from approximately 20:1 to approximately 50:1. Therefore, etching a dielectric layer with such an etch chemistry may terminate upon exposing an upper surface of the barrier layer. As such, a thickness of a barrier layer used to protect an underlying layer may be reduced to, for example, approximately 100 angstroms to approximately 150 angstroms. In addition, critical dimensions of contact openings formed with such an etch chemistry may be substantially uniform across a wafer. Furthermore, critical dimensions of contact openings formed with such an etch chemistry may be uniform from wafer to wafer.

Abstract translation: 提供了一种蚀刻形成在阻挡层上的介电层的方法，该介电层具有包括C x H y F z的蚀刻化学性质，其中x> = 2，y> = 2和z> = 2。 这种蚀刻化学物质可能对阻挡层是选择性的。 例如，蚀刻化学可以具有至少约20:1的介电层：阻挡层选择性，但可以在约20:1至约50:1的范围内。 因此，用这种蚀刻化学物质蚀刻电介质层可能在暴露阻挡层的上表面时终止。 因此，用于保护下层的阻挡层的厚度可以减小到例如大约100埃到大约150埃。 此外，用这种蚀刻化学品形成的接触开口的临界尺寸在晶片上基本上是均匀的。 此外，由这种蚀刻化学品形成的接触开口的临界尺寸可以从晶片到晶片均匀。

公开(公告)号：US20090179253A1

公开(公告)日：2009-07-16

申请号：US11811958

申请日：2007-06-13

Applicant: Sagy Levy ,  Krishnaswamy Ramkumar ,  Fredrick Jenne ,  Sam Geha

Inventor： Sagy Levy ,  Krishnaswamy Ramkumar ,  Fredrick Jenne ,  Sam Geha

IPC: H01L29/792 ,  H01L21/336

CPC classification number: H01L21/0214 ,  C23C16/0272 ,  C23C16/308 ,  G11C16/0466 ,  H01L21/02164 ,  H01L21/022 ,  H01L21/02211 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/02271 ,  H01L21/3145 ,  H01L27/11568 ,  H01L29/40117 ,  H01L29/518 ,  H01L29/7833 ,  H01L29/792

Abstract: A semiconductor device including an oxide-nitride-oxide (ONO) structure having a multi-layer charge storing layer and methods of forming the same are provided. Generally, the method involves: (i) forming a first oxide layer of the ONO structure; (ii) forming a multi-layer charge storing layer comprising nitride on a surface of the first oxide layer; and (iii) forming a second oxide layer of the ONO structure on a surface of the multi-layer charge storing layer. Preferably, the charge storing layer comprises at least two silicon oxynitride layers having differing stoichiometric compositions of Oxygen, Nitrogen and/or Silicon. More preferably, the ONO structure is part of a silicon-oxide-nitride-oxide-silicon (SONOS) structure and the semiconductor device is a SONOS memory transistor. Other embodiments are also disclosed.

Abstract translation: 提供了包括具有多层电荷存储层的氧化物 - 氧化物 - 氧化物（ONO）结构的半导体器件及其形成方法。 通常，该方法包括：（i）形成ONO结构的第一氧化物层; （ii）在所述第一氧化物层的表面上形成包含氮化物的多层电荷存储层; 和（iii）在多层电荷存储层的表面上形成ONO结构的第二氧化物层。 优选地，电荷存储层包括至少两个氧氮，氮和/或硅具有不同化学计量组成的氮氧化硅层。 更优选地，ONO结构是氧化硅 - 氧化物 - 氧化物 - 硅（SONOS）结构的一部分，并且半导体器件是SONOS存储晶体管。 还公开了其他实施例。

公开(公告)号：US20080293207A1

公开(公告)日：2008-11-27

申请号：US12125864

申请日：2008-05-22

Applicant: William W.C. Koutny, JR. ,  Sam Geha ,  Igor Kouznetsov ,  Krishnaswamy Ramkumar ,  Fredrick B. Jenne ,  Sagy Levy ,  Ravindra Kapre ,  Jeremy Warren

Inventor： William W.C. Koutny, JR. ,  Sam Geha ,  Igor Kouznetsov ,  Krishnaswamy Ramkumar ,  Fredrick B. Jenne ,  Sagy Levy ,  Ravindra Kapre ,  Jeremy Warren

IPC: H01L21/336

CPC classification number: H01L29/7833 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823462 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7836 ,  H01L29/7843

Abstract: A semiconductor structure and method to form the same. The semiconductor structure includes a substrate having a non-volatile charge trap memory device disposed on a first region and a logic device disposed on a second region. A charge trap dielectric stack may be formed subsequent to forming wells and channels of the logic device. HF pre-cleans and SC1 cleans may be avoided to improve the quality of a blocking layer of the non-volatile charge trap memory device. The blocking layer may be thermally reoxidized or nitridized during a thermal oxidation or nitridation of a logic MOS gate insulator layer to densify the blocking layer. A multi-layered liner may be utilized to first offset a source and drain implant in a high voltage logic device and also block silicidation of the nonvolatile charge trap memory device.

Abstract translation: 一种半导体结构及其形成方法。 半导体结构包括具有设置在第一区域上的非易失性电荷陷阱存储器件和设置在第二区域上的逻辑器件的衬底。 可以在形成逻辑器件的阱和通道之后形成电荷陷阱电介质叠层。 可以避免HF预清洗和SC1清洁，以提高非挥发性电荷陷阱存储器件的阻挡层的质量。 在逻辑MOS栅极绝缘体层的热氧化或氮化期间，阻挡层可以被热再氧化或氮化，以致密封阻挡层。 可以使用多层衬垫来首先在高压逻辑器件中偏置源极和漏极注入，并且还阻挡非易失性电荷陷阱存储器件的硅化。

公开(公告)号：US06756315B1

公开(公告)日：2004-06-29

申请号：US09672836

申请日：2000-09-29

Applicant: Hanna Bamnolker ,  Prashant Phatak ,  Usha Raghuram ,  Sam Geha

Inventor： Hanna Bamnolker ,  Prashant Phatak ,  Usha Raghuram ,  Sam Geha

IPC: H01L21302

CPC classification number: H01L21/02063 ,  H01L21/76802 ,  H01L21/76814

Abstract: The present invention provides a method of forming, in semiconductor substrates, contact openings having low contact resistance. The method involves, in particular, the introduction of a “soft etch” cleaning step that is used to clean the bottom of the contact openings. The “soft etch” cleaning step uses fluorocarbon chemistry. It is shown that the resulting resistance of the contact openings is reduced.

Abstract translation: 本发明提供了一种在半导体衬底中形成具有低接触电阻的接触开口的方法。 该方法特别涉及引入用于清洁接触开口底部的“软蚀刻”清洁步骤。 “软蚀刻”清洁步骤使用碳氟化合物。 显示出所产生的接触开口的电阻降低。

公开(公告)号：US5977638A

公开(公告)日：1999-11-02

申请号：US754521

申请日：1996-11-21

Applicant: T. J. Rodgers ,  Sam Geha ,  Chris Petti ,  Ting-Pwu Yen

Inventor： T. J. Rodgers ,  Sam Geha ,  Chris Petti ,  Ting-Pwu Yen

IPC: H01L21/3205 ,  H01L21/768 ,  H01L21/8244 ,  H01L23/528 ,  H01L27/11 ,  H01L23/48 ,  H01L21/44

CPC classification number: H01L27/11 ,  H01L21/32051 ,  H01L21/76838 ,  H01L21/76885 ,  H01L23/528 ,  H01L27/1104 ,  H01L2924/0002

Abstract: A method of forming edge metal lines to interconnect features in a semiconductor device. One embodiment comprises the steps of: patterning a first insulating layer to form a first feature having a first sidewall; depositing a metal layer over the first feature; and etching the metal layer so that a first edge metal line is formed adjacent to the first sidewall. The edge metal line may be substantially anisotropically etched to form the edge metal line. The edge metal line may comprise a plurality of metal layers. The edge metal line may also interconnect features in a semiconductor device (e.g., contacts). The method may further comprise the step of forming a protective coating over a portion of the metal layer such that the etching step may form a metal interconnect line and the edge metal line from the same metal layer. The metal interconnect line may comprise a bus that may have more current carrying capacity than the edge metal line.

Abstract translation: 一种形成边缘金属线以在半导体器件中互连特征的方法。 一个实施例包括以下步骤：图案化第一绝缘层以形成具有第一侧壁的第一特征; 在第一特征上沉积金属层; 并且蚀刻所述金属层，使得与所述第一侧壁相邻地形成第一边缘金属线。 边缘金属线可以被基本上各向异性地蚀刻以形成边缘金属线。 边缘金属线可以包括多个金属层。 边缘金属线还可以互连半导体器件（例如，触点）中的特征。 该方法还可以包括在金属层的一部分上形成保护涂层的步骤，使得蚀刻步骤可以从同一金属层形成金属互连线和边缘金属线。 金属互连线可以包括可以具有比边缘金属线更多的载流能力的总线。