公开(公告)号：US06756315B1

公开(公告)日：2004-06-29

申请号：US09672836

申请日：2000-09-29

申请人： Hanna Bamnolker ,  Prashant Phatak ,  Usha Raghuram ,  Sam Geha

发明人： Hanna Bamnolker ,  Prashant Phatak ,  Usha Raghuram ,  Sam Geha

IPC分类号： H01L21302

CPC分类号： H01L21/02063 ,  H01L21/76802 ,  H01L21/76814

摘要： The present invention provides a method of forming, in semiconductor substrates, contact openings having low contact resistance. The method involves, in particular, the introduction of a “soft etch” cleaning step that is used to clean the bottom of the contact openings. The “soft etch” cleaning step uses fluorocarbon chemistry. It is shown that the resulting resistance of the contact openings is reduced.

摘要翻译： 本发明提供了一种在半导体衬底中形成具有低接触电阻的接触开口的方法。 该方法特别涉及引入用于清洁接触开口底部的“软蚀刻”清洁步骤。 “软蚀刻”清洁步骤使用碳氟化合物。 显示出所产生的接触开口的电阻降低。

公开(公告)号：US08093128B2

公开(公告)日：2012-01-10

申请号：US12125864

申请日：2008-05-22

申请人： William W. C. Koutny, Jr. ,  Sam Geha ,  Igor Kouznetsov ,  Krishnaswamy Ramkumar ,  Fredrick B. Jenne ,  Sagy Levy ,  Ravindra Kapre ,  Jeremy Warren

发明人： William W. C. Koutny, Jr. ,  Sam Geha ,  Igor Kouznetsov ,  Krishnaswamy Ramkumar ,  Fredrick B. Jenne ,  Sagy Levy ,  Ravindra Kapre ,  Jeremy Warren

IPC分类号： H01L29/792

CPC分类号： H01L29/7833 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823462 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7836 ,  H01L29/7843

摘要： A semiconductor structure and method to form the same. The semiconductor structure includes a substrate having a non-volatile charge trap memory device disposed on a first region and a logic device disposed on a second region. A charge trap dielectric stack may be formed subsequent to forming wells and channels of the logic device. HF pre-cleans and SC1 cleans may be avoided to improve the quality of a blocking layer of the non-volatile charge trap memory device. The blocking layer may be thermally reoxidized or nitridized during a thermal oxidation or nitridation of a logic MOS gate insulator layer to densify the blocking layer. A multi-layered liner may be utilized to first offset a source and drain implant in a high voltage logic device and also block silicidation of the nonvolatile charge trap memory device.

公开(公告)号：US06756302B1

公开(公告)日：2004-06-29

申请号：US09688817

申请日：2000-10-17

申请人： Ende Shan ,  Gorley Lau ,  Sam Geha

发明人： Ende Shan ,  Gorley Lau ,  Sam Geha

IPC分类号： H01L2144

CPC分类号： H01L21/76843 ,  H01L21/2855 ,  H01L21/76876 ,  H01L21/76882

摘要： The invention concerns a method of forming a layer of metal on a substrate and fill the via with high throughput. A layer of metal can be formed on a substrate using sequentially a cold deposition step, a slow hot deposition step and a rapid hot deposition step. The cold deposition step need only be performed for a time sufficient to deposit a seed layer of metal over the entire surface on which the metal layer is to be formed. In the slow hot deposition step, further metal is deposited at a power allowing for surface diffusion of the deposited metal, which is then followed by a rapid hot deposition of metal under bulk diffusion conditions.

摘要翻译： 本发明涉及在衬底上形成金属层并以高生产量填充通孔的方法。 可以依次使用冷沉积步骤，慢速热沉积步骤和快速热沉积步骤，在衬底上形成金属层。 冷沉积步骤仅需要进行一段足以在其上形成金属层的整个表面上沉积金属种子层的时间。 在慢热沉积步骤中，以能够沉积金属的表面扩散的功率沉积另外的金属，然后在体积扩散条件下快速热沉积金属。

公开(公告)号：US6140228A

公开(公告)日：2000-10-31

申请号：US970107

申请日：1997-11-13

申请人： Ende Shan ,  Gorley Lau ,  Sam Geha

发明人： Ende Shan ,  Gorley Lau ,  Sam Geha

IPC分类号： H01L21/285 ,  H01L21/768 ,  H01L21/44

CPC分类号： H01L21/76843 ,  H01L21/2855 ,  H01L21/76876 ,  H01L21/76882

摘要： The invention concerns a method of forming a layer of metal on a substrate and fill the via with high throughput. A layer of metal can be formed on a substrate using sequentially a cold deposition step, a slow hot deposition step and a rapid hot deposition step. The cold deposition step need only be performed for a time sufficient to deposit a seed layer of metal over the entire surface on which the metal layer is to be formed. In the slow hot deposition step, further metal is deposited at a low power allowing for surface diffusion of the deposited metal, which is then followed by a rapid hot deposition of metal under bulk diffusion conditions.

摘要翻译： 本发明涉及在衬底上形成金属层并以高生产量填充通孔的方法。 可以依次使用冷沉积步骤，慢速热沉积步骤和快速热沉积步骤，在衬底上形成金属层。 冷沉积步骤仅需要进行一段足以在其上形成金属层的整个表面上沉积金属种子层的时间。 在慢热沉积步骤中，以低功率沉积另外的金属，允许沉积的金属的表面扩散，然后在体扩散条件下快速热沉积金属。

公开(公告)号：US20130175504A1

公开(公告)日：2013-07-11

申请号：US13436872

申请日：2012-03-31

申请人： Sagy Levy ,  Krishnaswamy Ramkumar ,  Fredrick Jenne ,  Sam Geha

发明人： Sagy Levy ,  Krishnaswamy Ramkumar ,  Fredrick Jenne ,  Sam Geha

IPC分类号： H01L29/775

CPC分类号： H01L29/66833 ,  B82Y10/00 ,  G11C16/0466 ,  G11C16/10 ,  G11C16/14 ,  H01L21/28282 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/4234 ,  H01L29/42392 ,  H01L29/66795 ,  H01L29/7833 ,  H01L29/792 ,  H01L29/7926

摘要： An embodiment of a semiconductor memory device including a multi-layer charge storing layer and methods of forming the same are described. Generally, the device includes a channel formed from a semiconducting material overlying a surface on a substrate connecting a source and a drain of the memory device; a tunnel oxide layer overlying the channel; and a multi-layer charge storing layer including an oxygen-rich, first oxynitride layer on the tunnel oxide layer in which a stoichiometric composition of the first oxynitride layer results in it being substantially trap free, and an oxygen-lean, second oxynitride layer on the first oxynitride layer in which a stoichiometric composition of the second oxynitride layer results in it being trap dense. In one embodiment, the device comprises a non-planar transistor including a gate having multiple surfaces abutting the channel, and the gate comprises the tunnel oxide layer and the multi-layer charge storing layer.

摘要翻译： 描述了包括多层电荷存储层的半导体存储器件的实施例及其形成方法。 通常，该器件包括由半导体材料形成的沟道，该半导体材料覆盖连接存储器件的源极和漏极的衬底上的表面; 覆盖通道的隧道氧化物层; 以及多层电荷存储层，其在所述隧道氧化物层上包含富氧的第一氧氮化物层，其中所述第一氧氮化物层的化学计量组成导致其基本上无陷阱，并且将贫氧的第二氮氧化物层置于 第一氧氮化物层，其中第二氧氮化物层的化学计量组成导致其陷阱致密。 在一个实施例中，该器件包括非平面晶体管，其包括具有邻接通道的多个表面的栅极，并且栅极包括隧道氧化物层和多层电荷存储层。

公开(公告)号：US07205164B1

公开(公告)日：2007-04-17

申请号：US11039301

申请日：2005-01-19

申请人： Sam Geha ,  Benjamin C. E. Schwarz ,  Chang Ju Choi ,  Biju Parameshwaran ,  Eugene Y. Chen ,  Helen L. Chung ,  Kamel Ounadjela ,  Witold Kula

发明人： Sam Geha ,  Benjamin C. E. Schwarz ,  Chang Ju Choi ,  Biju Parameshwaran ,  Eugene Y. Chen ,  Helen L. Chung ,  Kamel Ounadjela ,  Witold Kula

IPC分类号： H01L21/00

CPC分类号： H01L21/02071 ,  B82Y10/00 ,  H01L21/02063 ,  H01L43/12

摘要： Methods for patterning a magnetic cell junction and a topography used for and/or resulting from such methods are provided. In particular, a method is provided which includes etching portions of a topography adjacent to a patterned photoresist layer to a level within a cap film of the topography, removing etch residues from the topography and subsequently etching the remaining portions of the cap film to expose an uppermost magnetic layer. Another method is provided which includes patterning a dielectric mask layer above a patterned upper portion of a magnetic cell junction and ion milling a lower portion of the magnetic cell junction in alignment with the mask layer. An exemplary topography which may result and/or may be used for such methods includes a stack of layers having a dual layer cap film arranged above at least two magnetic layers spaced apart by a tunneling layer.

摘要翻译： 提供了用于图案化磁性细胞结的方法和用于和/或由这些方法产生的形貌。 特别地，提供了一种方法，其包括将与图案化的光致抗蚀剂层相邻的形貌的部分蚀刻到地形的盖膜内的水平，从形貌去除蚀刻残留物，随后蚀刻盖膜的剩余部分以暴露 最上层的磁性层。 提供了另一种方法，其包括将介电掩模层图案化在磁性细胞结的图案化的上部上方，并离子铣削与掩模层对准的磁性细胞结的下部。 可能导致和/或可用于这种方法的示例性形貌包括具有布置在至少两个由隧道层间隔开的磁性层之上的双层帽膜的层叠。

公开(公告)号：US5968851A

公开(公告)日：1999-10-19

申请号：US820893

申请日：1997-03-19

申请人： Sam Geha ,  Ende Shan

发明人： Sam Geha ,  Ende Shan

IPC分类号： H01L21/311 ,  H01L21/302

CPC分类号： H01L21/31111 ,  Y10S438/974

摘要： The present invention relates to a method of manufacturing an opening through a dielectric layer. The method comprises treating a polished dielectric layer with a wet etch selectively enchancing composition, such as buffered HF, prior to the formation of a patterned photoresist to improve the lateral-to-vertical wet etch ratio.

摘要翻译： 本发明涉及通过电介质层制造开口的方法。 该方法包括在形成图案化的光致抗蚀剂之前用湿蚀刻选择性增强组合物（例如缓冲HF）处理抛光的介电层，以改善横向到垂直的湿蚀刻比。

公开(公告)号：US08643124B2

公开(公告)日：2014-02-04

申请号：US13007533

申请日：2011-01-14

申请人： Sagy Levy ,  Krishnaswamy Ramkumar ,  Fredrick Jenne ,  Sam Geha

发明人： Sagy Levy ,  Krishnaswamy Ramkumar ,  Fredrick Jenne ,  Sam Geha

IPC分类号： H01L21/336

CPC分类号： H01L29/512 ,  C23C16/0272 ,  C23C16/308 ,  G11C16/0466 ,  H01L21/0214 ,  H01L21/02271 ,  H01L21/28282 ,  H01L21/3145 ,  H01L29/518 ,  H01L29/66833 ,  H01L29/7833 ,  H01L29/792

摘要： A semiconductor device including a silicon-oxide-oxynitride-oxide-silicon structure and methods of forming the same are provided. Generally, the structure comprises: a tunnel oxide layer on a surface of a substrate including silicon; a multi-layer charge storing layer including an oxygen-rich, first oxynitride layer on the tunnel oxide layer in which the stoichiometric composition of the first oxynitride layer results in it being substantially trap free, and an oxygen-lean, second oxynitride layer on the first oxynitride layer in which the stoichiometric composition of the second oxynitride layer results in it being trap dense; a blocking oxide layer on the second oxynitride layer; and a silicon containing gate layer on the blocking oxide layer. Other embodiments are also disclosed.

摘要翻译： 提供了包括氧化硅 - 氧氮化物 - 氧化物 - 硅结构的半导体器件及其形成方法。 通常，该结构包括：在包括硅的衬底的表面上的隧道氧化物层; 多层电荷存储层，其包括在所述隧道氧化物层上的富氧第一氧氮化物层，其中所述第一氧氮化物层的化学计量组成导致其基本上不含杂质，并且所述第二氧氮化物层 第一氮氧化物层，其中第二氮氧化物层的化学计量组成导致其陷阱致密; 在第二氮氧化物层上的阻挡氧化物层; 以及在所述阻挡氧化物层上的含硅栅极层。 还公开了其他实施例。

公开(公告)号：US06803318B1

公开(公告)日：2004-10-12

申请号：US09661666

申请日：2000-09-14

申请人： Jianmin Qiao ,  Sam Geha ,  Mehran G. Sedigh

发明人： Jianmin Qiao ,  Sam Geha ,  Mehran G. Sedigh

IPC分类号： H01L2124

CPC分类号： H01L21/76897 ,  H01L21/31116 ,  H01L21/76801 ,  H01L21/76802

摘要： A method is provided for forming a self aligned contact by etching an opening through a low doped or undoped dielectric layer such as phosphosilicate glass. The dielectric layer may be formed on a semiconductor layer which may include regions of monocrystalline silicon and undoped silicon dioxide. A first portion of a dielectric layer may be etched with a first etch chemistry, and a second portion of the dielectric layer may be etched with a second etch chemistry. The first etch chemistry may be substantially different than the second etch chemistry. In this manner, the first etch chemistry may have a substantially different etch selectivity than the second etch chemistry. For example, in an embodiment, the first etch chemistry may be selective to silicon nitride, and the second etch chemistry may be selective to undoped silicon oxide. Therefore, by using multiple etch chemistries to etch a single dielectric layer, a self aligned contact having optimized properties such as sidewall angle, aspect ratio, and critical dimension may be formed while an etch stop liner layer such as a silicon nitride layer may be eliminated.

摘要翻译： 提供了一种通过蚀刻通过低掺杂或未掺杂的介电层（例如磷硅玻璃）的开口来形成自对准接触的方法。 电介质层可以形成在可以包括单晶硅和未掺杂二氧化硅的区域的半导体层上。 介电层的第一部分可以用第一蚀刻化学品进行蚀刻，并且可以用第二蚀刻化学物质蚀刻介电层的第二部分。 第一蚀刻化学物质可能与第二蚀刻化学物质基本不同。 以这种方式，第一蚀刻化学物质可能具有与第二蚀刻化学物质基本不同的蚀刻选择性。 例如，在一个实施方案中，第一蚀刻化学物质可以对氮化硅是选择性的，并且第二蚀刻化学物质可以对未掺杂的氧化硅是选择性的。 因此，通过使用多个蚀刻化学品来蚀刻单个电介质层，可以形成具有优化性能如侧壁角，纵横比和临界尺寸的自对准接触，同时可以消除诸如氮化硅层的蚀刻停止衬垫层 。

公开(公告)号：US09449831B2

公开(公告)日：2016-09-20

申请号：US13436872

申请日：2012-03-31

申请人： Sagy Levy ,  Krishnaswamy Ramkumar ,  Fredrick Jenne ,  Sam Geha

发明人： Sagy Levy ,  Krishnaswamy Ramkumar ,  Fredrick Jenne ,  Sam Geha

IPC分类号： H01L21/28 ,  G11C16/04 ,  H01L29/792 ,  B82Y10/00 ,  H01L29/423 ,  H01L29/78

CPC分类号： H01L29/66833 ,  B82Y10/00 ,  G11C16/0466 ,  G11C16/10 ,  G11C16/14 ,  H01L21/28282 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/4234 ,  H01L29/42392 ,  H01L29/66795 ,  H01L29/7833 ,  H01L29/792 ,  H01L29/7926

摘要： An embodiment of a semiconductor memory device including a multi-layer charge storing layer and methods of forming the same are described. Generally, the device includes a channel formed from a semiconducting material overlying a surface on a substrate connecting a source and a drain of the memory device; a tunnel oxide layer overlying the channel; and a multi-layer charge storing layer including an oxygen-rich, first oxynitride layer on the tunnel oxide layer in which a stoichiometric composition of the first oxynitride layer results in it being substantially trap free, and an oxygen-lean, second oxynitride layer on the first oxynitride layer in which a stoichiometric composition of the second oxynitride layer results in it being trap dense. In one embodiment, the device comprises a non-planar transistor including a gate having multiple surfaces abutting the channel, and the gate comprises the tunnel oxide layer and the multi-layer charge storing layer.

摘要翻译： 描述了包括多层电荷存储层的半导体存储器件的实施例及其形成方法。 通常，该器件包括由半导体材料形成的沟道，该半导体材料覆盖连接存储器件的源极和漏极的衬底上的表面; 覆盖通道的隧道氧化物层; 以及多层电荷存储层，其在所述隧道氧化物层上包含富氧的第一氧氮化物层，其中所述第一氧氮化物层的化学计量组成导致其基本上无陷阱，并且将贫氧的第二氮氧化物层置于 第一氧氮化物层，其中第二氧氮化物层的化学计量组成导致其陷阱致密。 在一个实施例中，该器件包括非平面晶体管，其包括具有邻接通道的多个表面的栅极，并且栅极包括隧道氧化物层和多层电荷存储层。