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公开(公告)号：US10812088B2
公开(公告)日：2020-10-20
申请号：US16220898
申请日：2018-12-14
Applicant: Samsung Electronics Co., Ltd.
Inventor： Zhiqiang Huang , Chih-Wei Yao , Hiep Pham
IPC: H03L7/087 , H04L27/227 , H03L7/08 , H03L7/10
Abstract: A synchronized in-phase/quadrature phase (I/Q) detection circuit and a method of the same are provided. The synchronized I/Q detection circuit includes a first logic circuit; a first filter; a first reset and sampling circuit; a first multiplexer; a second logic circuit; a second filter; a second reset and sampling circuit; a signal generator; and a comparator.
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公开(公告)号：US10725432B2
公开(公告)日：2020-07-28
申请号：US16040963
申请日：2018-07-20
Applicant: Samsung Electronics Co., Ltd.
Inventor： Chih-Wei Yao , Ronghua Ni
Abstract: A system and method for fast converging gain calibration for phase lock loops (PLL) are herein disclosed. According to one embodiment, a method includes receiving, with a voltage generation circuit, an input value representing a difference between a sampled voltage and a reference voltage, and adjusting, with the voltage generation circuit, the reference voltage by generating a voltage output based on the difference represented by the input value.
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公开(公告)号：US10009036B2
公开(公告)日：2018-06-26
申请号：US15430163
申请日：2017-02-10
Applicant: Samsung Electronics Co., Ltd.
Inventor： Wing-Fai Loke , Chih-Wei Yao
CPC classification number: H03M1/1009 , H03L7/0995 , H03L7/0996 , H03L7/0998 , H03M1/183
Abstract: An apparatus and a method. The apparatus includes a counter array; a ring oscillator that is electrically coupled to the counter array, where the counter array counts a number of cycles in the ring oscillator; an analog-to-digital converter (ADC) driver that is electrically coupled to the ring oscillator; and an ADC that is electrically coupled to the ADC driver, where an output of the ADC is electrically coupled to the ring oscillator.
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公开(公告)号：US20160276978A1
公开(公告)日：2016-09-22
申请号：US15167040
申请日：2016-05-27
Applicant: Samsung Electronics Co., Ltd.
Inventor： Wing Fai Loke , Chih-Wei Yao , Sunghwan Kim
IPC: H03B5/12
CPC classification number: H03B5/124 , H03B5/1212 , H03B5/1215 , H03B5/1225 , H03B5/1243 , H03J2200/10
Abstract: Methods, apparatuses, and systems for providing a variable output using an array of cells are discussed. In the fine tuning bank of an apparatus, control is implemented by selecting a boundary cell from the array of cells and having every cell before the boundary cell in a circuit path be grounded and having the boundary cell and every cell after the boundary cell in the circuit path be connected to a voltage source. The circuit path may be the one formed by using thermometer coding in the fine tuning bank.
Abstract translation: 讨论了使用单元阵列提供可变输出的方法，装置和系统。 在设备的微调库中，通过从单元阵列中选择边界单元并且使电路中的边界单元之前的每个单元接地并且在边界单元之后具有边界单元和边界单元之后的每个单元，来实现控制 电路路径连接到电压源。 电路路径可以是在微调库中使用温度计编码形成的路径。
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15.发明申请公开(公告)号：US20160079918A1
公开(公告)日：2016-03-17
申请号：US14593251
申请日：2015-01-09
Applicant: Samsung Electronics Co., Ltd.
Inventor： Wing Fai LOKE , Chih-Wei Yao
CPC classification number: H03B5/04 , H03B5/1215 , H03B5/1237 , H03B5/1243 , H03B2201/0208
Abstract: A system using temperature tracking for a controlled oscillator (CO) is provided. The system includes at least one coarse tuning capacitor circuit including a plurality of selectable coarse tuning capacitors operable in at least three modes of operation, thereby allowing switching between each coarse capacitor of the plurality of selectable coarse capacitors when a selected coarse tuning capacitor has reached one of its high tuning range and low tuning range.
Abstract translation: 提供了一种使用受控振荡器（CO）温度跟踪的系统。 该系统包括至少一个粗调谐电容器电路，其包括可在至少三种工作模式下操作的多个可选择的粗调谐电容器，从而允许当所选择的粗调谐电容器达到一个时，在多个可选粗略电容器的每个粗电容器之间切换 的高调谐范围和低调谐范围。
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Patent Agency Ranking
16.发明授权公开(公告)号：US11431344B2
公开(公告)日：2022-08-30
申请号：US17354545
申请日：2021-06-22
Applicant: Samsung Electronics Co., Ltd.
Inventor： Yongrong Zuo , Chih-Wei Yao , Wanghua Wu
IPC: H03L7/099 , H03K17/687 , H04L7/033 , H01L29/78
Abstract: An apparatus and method are provided. The apparatus includes a phase locked loop (PLL) configured to generate a reference signal; a sub-sampling PLL (SS-PLL) connected to the PLL and configured to sub-sample the reference signal; and a first pre-charge circuit connected to a sampling device of the SS-PLL and configured to facilitate frequency locking of the SS-PLL.
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公开(公告)号：US11233627B2
公开(公告)日：2022-01-25
申请号：US17070577
申请日：2020-10-14
Applicant: Samsung Electronics Co., Ltd.
Inventor： Zhiqiang Huang , Hiep Pham , Chih-Wei Yao
Abstract: An apparatus for providing fast-settling quadrature detection and correction includes: a quadrature correction circuit that receives four quadrature clock signals; a quadrature detector that selects two clock signals among the four quadrature clock signals; and a phase digitizer that generates a digital code indicating a phase difference between the two clock signals. The quadrature correction circuit adjusts a phase between the two clock signals using the digital code.
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18.发明授权公开(公告)号：US11063599B2
公开(公告)日：2021-07-13
申请号：US16516581
申请日：2019-07-19
Applicant: Samsung Electronics Co., Ltd.
Inventor： Yongrong Zuo , Chih-Wei Yao , Wanghua Wu
IPC: H03L7/099 , H03K17/687 , H04L7/033 , H01L29/78
Abstract: An apparatus and method are provided. The apparatus includes a phase locked loop (PLL) configured to generate a reference signal; a sub-sampling PLL (SS-PLL) connected to the PLL and configured to sub-sample the reference signal; and a first pre-charge circuit connected to the SS-PLL and configured to allow an output voltage of the SS-PLL to transition to an operating voltage to indicate that a difference between two voltage inputs is zero on average.
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公开(公告)号：US11050428B2
公开(公告)日：2021-06-29
申请号：US17010322
申请日：2020-09-02
Applicant: Samsung Electronics Co., Ltd.
Inventor： Zhiqiang Huang , Chih-Wei Yao , Hiep Pham
IPC: H03L7/087 , H04L27/227 , H03L7/08 , H03L7/10
Abstract: A synchronized I/Q detection circuit is provided. A first subset of input signals and, subsequently, a second subset of input signals are provided by a first multiplexer and received by a first phase detector. Outputs of the first phase detector are receiving, by a first reset and sampling circuit. A second set of input signals are provided by a second multiplexer and received by a second phase detector, from a second multiplexer, while the first multiplexer receives the first and second subsets of input signals. The first subset of input signals has a same phase order as the second set of input signals, and the second subset of input signals has a different phase order than the second set of input signals. Outputs of the second phase detector are received by a second reset and sampling circuit. A comparator outputs a detected phase difference based on the outputs of the first and second reset and sampling circuits.
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20.发明授权公开(公告)号：US10965297B1
公开(公告)日：2021-03-30
申请号：US16890757
申请日：2020-06-02
Applicant: Samsung Electronics Co., Ltd.
Inventor： Wanghua Wu , Chih-Wei Yao
Abstract: Methods and apparatuses are provided for fractional-N frequency synthesis using a phase-locked loop (PLL). A phase detector (PD) of the PLL determines a phase difference between a clock and a feedback clock (CLKFB). A low-pass loop filter of the PLL detects a control voltage based on the phase difference. A voltage-controlled oscillator (VCO) of the PLL generates a periodic signal based on the control voltage. A sigma-delta modulator (SDM) of the PLL generates a division sequence ratio and a selection control signal based on a frequency command word. A multi-modulus divider (MMDIV) generates a first CLKFB and a second CLKFB based on the division sequence ratio and differential inputs of the periodic signal. The MMDIV outputs one of the first CLKFB and the second CLKFB as the CLKFB to the PD based on the selection control signal.
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