公开(公告)号：US20220084993A1

公开(公告)日：2022-03-17

申请号：US17239956

申请日：2021-04-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： DONGKYU KIM ,  SEOKHYUN LEE ,  YEONHO JANG ,  JAEGWON JANG

IPC: H01L25/10 ,  H01L23/00 ,  H01L23/31 ,  H01L23/538 ,  H01L21/683 ,  H01L21/48 ,  H01L21/56 ,  H01L25/00

Abstract: A semiconductor package device includes a first semiconductor package, a second semiconductor package, and first connection terminals between the first and second semiconductor packages. The first semiconductor package includes a lower redistribution substrate, a semiconductor chip, and an upper redistribution substrate vertically spaced apart from the lower redistribution substrate across the semiconductor chip. The upper redistribution substrate includes a dielectric layer, redistribution patterns vertically stacked in the dielectric layer and each including line and via parts, and bonding pads on uppermost redistribution patterns. The bonding pads are exposed from the dielectric layer and in contact with the first connection terminals. A diameter of each bonding pad decreases in a first direction from a central portion at a top surface of the upper redistribution substrate to an outer portion at the top surface thereof. A thickness of each bonding pad increases in the first direction.

公开(公告)号：US20210398890A1

公开(公告)日：2021-12-23

申请号：US17177305

申请日：2021-02-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： DONGKYU KIM ,  SEOKHYUN LEE ,  KYOUNG LIM SUK ,  JAEGWON JANG ,  GWANGJAE JEON

IPC: H01L23/498 ,  H01L23/00 ,  H01L25/065

Abstract: A semiconductor package may include a redistribution substrate, a connection terminal, and a semiconductor chip sequentially stacked. The redistribution substrate may include an insulating layer, a plurality of redistribution patterns, which are vertically stacked in the insulating layer, and each of which includes interconnection and via portions, and a bonding pad on the interconnection portion of the topmost redistribution pattern. The topmost redistribution pattern and the bonding pad may include different metallic materials. The bonding pad may have first and second surfaces opposite to each other. The first surface of the bonding pad may be in contact with a top surface of the interconnection portion of the topmost redistribution pattern. A portion of the second surface of the bonding pad may be in contact with the connection terminal. The insulating layer may be extended to be in contact with the remaining portion of the second surface.

公开(公告)号：US20240178114A1

公开(公告)日：2024-05-30

申请号：US18227348

申请日：2023-07-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： KYOUNG LIM SUK ,  DONGKYU KIM ,  JI HWANG KIM ,  HYEONJEONG HWANG

IPC: H01L23/498 ,  H01L21/56 ,  H01L23/00

CPC classification number: H01L23/49816 ,  H01L21/565 ,  H01L21/568 ,  H01L23/49822 ,  H01L24/16 ,  H01L24/32 ,  H01L2224/16055 ,  H01L2224/16227 ,  H01L2224/32146 ,  H01L2224/32235 ,  H01L2924/1435 ,  H01L2924/15311 ,  H01L2924/351

Abstract: Disclosed are semiconductor packages and their fabrication methods. The semiconductor package comprises a lower semiconductor chip on a first redistribution substrate and including a through via, a lower molding layer on the first redistribution substrate and surrounding the lower semiconductor chip, a lower post on the first redistribution substrate and laterally spaced apart from the lower semiconductor chip, an upper semiconductor chip on the lower semiconductor chip and coupled to the through via, an upper molding layer on the lower molding layer and surrounding the upper semiconductor chip, an upper post on the lower molding layer and laterally spaced apart from the upper semiconductor chip, and a second redistribution substrate on the upper molding layer and coupled to the upper post. A top surface of the lower molding layer is at a level higher than that of a top surface of the lower semiconductor chip.

公开(公告)号：US20240030119A1

公开(公告)日：2024-01-25

申请号：US18374396

申请日：2023-09-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： DONGKYU KIM ,  SEOKHYUN LEE ,  KYOUNG LIM SUK ,  JAEGWON JANG ,  GWANGJAE JEON

IPC: H01L23/498 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L23/49822 ,  H01L24/32 ,  H01L24/16 ,  H01L23/49833 ,  H01L25/0657 ,  H01L23/49894 ,  H01L2224/16227 ,  H01L2224/32225

Abstract: A semiconductor package may include a redistribution substrate, a connection terminal, and a semiconductor chip sequentially stacked. The redistribution substrate may include an insulating layer, a plurality of redistribution patterns, which are vertically stacked in the insulating layer, and each of which includes interconnection and via portions, and a bonding pad on the interconnection portion of the topmost redistribution pattern. The topmost redistribution pattern and the bonding pad may include different metallic materials. The bonding pad may have first and second surfaces opposite to each other. The first surface of the bonding pad may be in contact with a top surface of the interconnection portion of the topmost redistribution pattern. A portion of the second surface of the bonding pad may be in contact with the connection terminal. The insulating layer may be extended to be in contact with the remaining portion of the second surface.

公开(公告)号：US20230420402A1

公开(公告)日：2023-12-28

申请号：US18244462

申请日：2023-09-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： GWANGJAE JEON ,  DONGKYU KIM ,  JUNG-HO PARK ,  YEONHO JANG

IPC: H01L23/00 ,  H01L21/768 ,  H01L23/498 ,  H01L23/31

CPC classification number: H01L24/11 ,  H01L21/76885 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/05 ,  H01L23/3128 ,  H01L23/3114 ,  H01L24/13 ,  H01L2224/04105 ,  H01L2224/023 ,  H01L2224/0401

Abstract: Disclosed is a semiconductor package comprising a redistribution substrate, and a semiconductor chip on a top surface of the redistribution substrate. The redistribution substrate includes an under-bump pattern, a lower dielectric layer that covers a sidewall of the under-bump pattern, and a first redistribution pattern on the lower dielectric layer. The first redistribution pattern includes a first line part. A width at a top surface of the under-bump pattern is greater than a width at a bottom surface of the under-bump pattern. A thickness of the under-bump pattern is greater than a thickness of the first line part.

公开(公告)号：US20230230965A1

公开(公告)日：2023-07-20

申请号：US18125170

申请日：2023-03-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： DONGKYU KIM ,  SEOKHYUN LEE ,  YEONHO JANG ,  JAEGWON JANG

IPC: H01L25/10 ,  H01L23/00 ,  H01L21/56 ,  H01L23/538 ,  H01L21/48 ,  H01L25/00 ,  H01L23/31 ,  H01L21/683

CPC classification number: H01L25/105 ,  H01L24/19 ,  H01L21/563 ,  H01L23/562 ,  H01L23/5383 ,  H01L24/48 ,  H01L21/4857 ,  H01L25/50 ,  H01L21/565 ,  H01L23/3135 ,  H01L21/568 ,  H01L24/20 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/5386 ,  H01L21/4853 ,  H01L23/5389 ,  H01L2224/214 ,  H01L2225/1058 ,  H01L2225/1041 ,  H01L2225/1035 ,  H01L2924/3511 ,  H01L2924/01029 ,  H01L2221/68372 ,  H01L2224/48227 ,  H01L2924/01079 ,  H01L2924/01028 ,  H01L2224/215

Abstract: A semiconductor package device includes a first semiconductor package, a second semiconductor package, and first connection terminals between the first and second semiconductor packages. The first semiconductor package includes a lower redistribution substrate, a semiconductor chip, and an upper redistribution substrate vertically spaced apart from the lower redistribution substrate across the semiconductor chip. The upper redistribution substrate includes a dielectric layer, redistribution patterns vertically stacked in the dielectric layer and each including line and via parts, and bonding pads on uppermost redistribution patterns. The bonding pads are exposed from the dielectric layer and in contact with the first connection terminals. A diameter of each bonding pad decreases in a first direction from a central portion at a top surface of the upper redistribution substrate to an outer portion at the top surface thereof. A thickness of each bonding pad increases in the first direction.

公开(公告)号：US20220415771A1

公开(公告)日：2022-12-29

申请号：US17670635

申请日：2022-02-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： HYEONJEONG HWANG ,  DONGKYU KIM ,  MINJUNG KIM ,  YEONHO JANG

IPC: H01L23/498 ,  H01L23/31

Abstract: A semiconductor package including a redistribution substrate extending in a first direction and a second direction perpendicular to the first direction, a semiconductor chip mounted on a top surface of the redistribution substrate, and an outer terminal on a bottom surface of the redistribution substrate. The redistribution substrate may include an under-bump pattern, a redistribution insulating layer covering a top surface and a side surface of the under-bump pattern, a protection pattern interposed between the top surface of the under-bump pattern and the redistribution insulating layer, and interposed between the side surface of the under-bump pattern and the redistribution insulating layer, and a redistribution pattern on the under-bump pattern. The outer terminal may be disposed on a bottom surface of the under-bump pattern.