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    NON-VOLATILE MEMORY DEVICE AND METHOD OF OPERATING THE SAME
    11.
    发明申请
    NON-VOLATILE MEMORY DEVICE AND METHOD OF OPERATING THE SAME 有权

    公开(公告)号：US20240395335A1

    公开(公告)日：2024-11-28

    申请号：US18791943

    申请日：2024-08-01

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Dong-Hun Kwak

    IPC: G11C16/26 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/34 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H10B41/27 ,  H10B43/27

    Abstract: A method of operating a non-volatile memory device includes performing a first sensing operation on the non-volatile memory device during a first sensing time including a first section, a second section, and a third section. The performing of the first sensing operation includes applying a first voltage level, which is variable according to a first target voltage level, to a selected word line in the first section, applying a second voltage level, which is different from the first voltage level, to the selected word line in the second section, and applying the first target voltage level, which is different from the second voltage level, to the selected word line in the third section. The first voltage level becomes greater as the first target voltage level becomes greater.

    Non-volatile memory device and method of operating the same
    14.
    发明授权
    Non-volatile memory device and method of operating the same 有权

    公开(公告)号：US11276472B2

    公开(公告)日：2022-03-15

    申请号：US16935559

    申请日：2020-07-22

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Dong-Hun Kwak

    IPC: G11C16/26 ,  G11C16/08 ,  G11C16/10 ,  G11C16/34 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L27/11556 ,  H01L27/11582 ,  G11C16/04

    Abstract: A method of operating a non-volatile memory device includes performing a first sensing operation on the non-volatile memory device during a first sensing time including a first section, a second section, and a third section. The performing of the first sensing operation includes applying a first voltage level, which is variable according to a first target voltage level, to a selected word line in the first section, applying a second voltage level, which is different from the first voltage level, to the selected word line in the second section, and applying the first target voltage level, which is different from the second voltage level, to the selected word line in the third section. The first voltage level becomes greater as the first target voltage level becomes greater.

    Nonvolatile memory devices and memory systems
    15.
    发明授权
    Nonvolatile memory devices and memory systems 有权

    公开(公告)号：US10777254B2

    公开(公告)日：2020-09-15

    申请号：US16817951

    申请日：2020-03-13

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Dong-Hun Kwak ,  Hee-Woong Kang ,  Jun-Ho Seo ,  Hee-Won Lee

    IPC: G11C7/12 ,  G11C11/4074 ,  G11C16/30 ,  G11C16/10 ,  G11C16/06 ,  G11C16/04 ,  G11C11/56 ,  G11C11/4097 ,  G11C11/408 ,  G11C16/08 ,  G11C8/12 ,  G11C7/10 ,  G11C16/34

    Abstract: A nonvolatile memory device includes a memory cell array, a voltage generator, a page buffer circuit, a row decoder and a control circuit. The memory cell array includes a plurality of mats corresponding to different bit-lines. The voltage generator generates word-line voltages applied to the memory cell array. The page buffer circuit is coupled to the memory cell array through bit-lines. The row decoder is coupled to the memory cell array through word-lines, and the row decoder transfers the word-line voltages to the memory cell array. The control circuit controls the voltage generator, the row decoder and the page buffer circuit based on a command and an address. The control circuit selects a voltage between different voltages to apply the selected different voltages to at least one of the word-lines or at least one of the bit-lines according to a number of mats of the plurality mats, which operate simultaneously.

    NON-VOLATILE MEMORY DEVICE AND METHOD OF OPERATING THE SAME
    18.
    发明申请
    NON-VOLATILE MEMORY DEVICE AND METHOD OF OPERATING THE SAME 有权

    公开(公告)号：US20230019716A1

    公开(公告)日：2023-01-19

    申请号：US17949752

    申请日：2022-09-21

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Dong-Hun Kwak

    IPC: G11C16/26 ,  G11C16/04 ,  G11C16/10 ,  H01L27/11582 ,  H01L23/00 ,  H01L25/18 ,  G11C16/34 ,  H01L25/065 ,  G11C16/08 ,  H01L27/11556

    Abstract: A method of operating a non-volatile memory device includes performing a first sensing operation on the non-volatile memory device during a first sensing time including a first section, a second section, and a third section. The performing of the first sensing operation includes applying a first voltage level, which is variable according to a first target voltage level, to a selected word line in the first section, applying a second voltage level, which is different from the first voltage level, to the selected word line in the second section, and applying the first target voltage level, which is different from the second voltage level, to the selected word line in the third section. The first voltage level becomes greater as the first target voltage level becomes greater.

    Methods of erasing data in nonvolatile memory devices and nonvolatile memory devices performing the same
    19.
    发明授权
    Methods of erasing data in nonvolatile memory devices and nonvolatile memory devices performing the same 有权

    公开(公告)号：US11164637B2

    公开(公告)日：2021-11-02

    申请号：US17015525

    申请日：2020-09-09

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sang-Wan Nam ,  Dong-Hun Kwak ,  Chi-Weon Yoon

    IPC: G11C16/04 ,  G11C16/16 ,  G11C8/12 ,  H01L27/11573 ,  H01L27/11582 ,  G11C16/14

    Abstract: A nonvolatile memory device includes a memory cell region, a peripheral circuit region, a memory block in the memory cell region, and a control circuit in the peripheral circuit region. The memory cell region includes a first metal pad. The peripheral circuit region includes a second metal pad and is vertically connected to the memory cell region by the first metal pad and the second metal pad. The memory block includes a plurality of memory cells disposed in a vertical direction. The control circuit applies an erase voltage to an erase source terminal of the memory block, and applies a first voltage to a first selection line among a plurality of selection lines in the memory block. The first voltage is higher than the erase voltage. The first selection line is disposed closest to the erase source terminal among the plurality of selection lines and is used for selecting the memory block as an erase target block.

    Nonvolatile memory devices
    20.
    发明授权
    Nonvolatile memory devices 有权

    公开(公告)号：US11017838B2

    公开(公告)日：2021-05-25

    申请号：US16991693

    申请日：2020-08-12

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hee-Woong Kang ,  Dong-Hun Kwak ,  Jun-Ho Seo ,  Hee-Won Lee

    IPC: G11C7/12 ,  G11C11/4074 ,  G11C7/10 ,  G11C8/12 ,  G11C16/08 ,  G11C11/408 ,  G11C11/4097 ,  G11C11/56 ,  G11C16/04 ,  G11C16/06 ,  G11C16/10 ,  G11C16/30 ,  G11C16/34

    Abstract: A nonvolatile memory device includes a memory cell array and a row decoder. The memory cell array includes a plurality of mats. A first cell string of first mat is connected to a plurality of first word-lines, a first bit-line and a first string selection line. A second cell string of second mat is connected to a plurality of second word-lines, a second bit-line and a second string selection line. Each of the first and second cell strings includes a ground selection transistor, memory cells, and a string selection transistor coupled in series. The row decoder applies a first voltage to a third word-line among the plurality of first and second word-lines for a first period of time in a single mat mode and to apply a second voltage to the third word-line for a second period of time longer than the first period of time in a multi-mat mode.

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