公开(公告)号：US20240387486A1

公开(公告)日：2024-11-21

申请号：US18584905

申请日：2024-02-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dahee Kim ,  Hongwon Kim ,  Jae-Ean Lee ,  Taehoon Lee ,  Gyujin Choi

IPC: H01L25/16 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L23/498

Abstract: An example semiconductor package includes a substrate, a first semiconductor chip mounted on the substrate, a mold layer on the substrate to cover the first semiconductor chip, and outer terminals positioned below the substrate. The substrate includes a first interconnection layer, a second interconnection layer on the first interconnection layer, a passive device mounted on a bottom surface of the second interconnection layer, and a connection member at a side of the passive device and between the first interconnection layer and the second interconnection layer to connect the first interconnection layer to the second interconnection layer. The outer terminals are coupled to a bottom surface of the first interconnection layer, the passive device includes a first pad on a top surface of the passive device, and an interconnection pattern of the second interconnection layer contacts the first pad.

公开(公告)号：US20240347487A1

公开(公告)日：2024-10-17

申请号：US18368640

申请日：2023-09-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaeean Lee ,  Dahee Kim ,  Taehoon Lee ,  Gyujin Choi

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/498

CPC classification number: H01L24/05 ,  H01L23/3128 ,  H01L23/49822 ,  H01L23/49833 ,  H01L24/06 ,  H01L24/08 ,  H01L23/49838 ,  H01L24/03 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/03462 ,  H01L2224/05548 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/0601 ,  H01L2224/08225 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48225 ,  H01L2224/73265 ,  H01L2924/1815

Abstract: An upper redistribution wiring layer of a semiconductor package includes a protective layer provided on at least one upper insulating layer and having an opening that exposes at least a portion of an uppermost redistribution wiring among second redistribution wirings, and a bonding pad provided on the uppermost redistribution wiring through the opening. The bonding pad includes a first plating pattern formed on the uppermost redistribution wiring, the first plating pattern including a via pattern provided in the opening and a pad pattern formed on the via pattern to be exposed from the opening, a second plating pattern on the second plating pattern, and a third plating pattern on the second plating pattern.

公开(公告)号：US11972966B2

公开(公告)日：2024-04-30

申请号：US17007433

申请日：2020-08-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gyujin Choi ,  Changeun Joo

IPC: H01L21/768 ,  H01L21/48 ,  H01L21/56 ,  H01L21/66 ,  H01L21/68 ,  H01L23/00 ,  H01L23/31 ,  H01L23/495 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L21/68 ,  H01L21/4853 ,  H01L21/563 ,  H01L21/76838 ,  H01L22/34 ,  H01L24/11 ,  H01L24/14

Abstract: In a method of manufacturing a semiconductor package, a plurality of semiconductor chips are encapsulated in a carrier to provide encapsulated semiconductor chips. A first surface of the encapsulated semiconductor chips includes chip pads exposed from a first surface of the carrier. An alignment error of each of the semiconductor chips with respect to the carrier is measured. A redistribution wiring structure may be formed on the first surface of the carrier. Correction values for each layer of the redistribution wiring structure may be reflected while forming the redistribution wiring structure in order to correct the alignment error while forming the redistribution wiring structure. The redistribution wiring structure may have redistribution wirings electrically connected to the chip pads on the first surface of the carrier. Outer connection members may be formed on the redistribution wiring structure and may be configured to be electrically connected to the outermost redistribution wirings.

公开(公告)号：US20240063131A1

公开(公告)日：2024-02-22

申请号：US18203239

申请日：2023-05-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaeean Lee ,  Dahee Kim ,  Taehoon Lee ,  Gyujin Choi

IPC: H01L23/538 ,  H10B80/00 ,  H01L25/18 ,  H01L25/00 ,  H01L23/00

CPC classification number: H01L23/5385 ,  H10B80/00 ,  H01L25/18 ,  H01L25/50 ,  H01L24/19 ,  H01L24/20 ,  H01L24/32 ,  H01L24/29 ,  H01L2224/19 ,  H01L2224/211 ,  H01L24/16 ,  H01L2224/16227 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29194 ,  H01L2924/0665 ,  H01L2224/32225 ,  H01L24/73 ,  H01L2224/73204 ,  H01L24/33 ,  H01L2224/33181 ,  H01L2224/73267 ,  H01L2224/32221 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1443 ,  H01L2924/1441 ,  H01L2924/14335 ,  H01L23/3128

Abstract: A semiconductor package includes a first substrate having a first surface and a second surface, and having a cavity extending from the first surface to the second surface in a vertical direction, a first chip disposed in the cavity of the first substrate, a redistribution structure on the first surface of the first substrate, a second chip on the redistribution structure, a third chip spaced apart from the second chip in a horizontal direction and disposed on the redistribution structure, and a bridge chip embedded in the redistribution structure, wherein the redistribution structure includes a first redistribution pattern, a second redistribution pattern, and a third redistribution pattern.

公开(公告)号：US20230207508A1

公开(公告)日：2023-06-29

申请号：US18170857

申请日：2023-02-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Changeun Joo ,  Gyujin Choi

IPC: H01L23/00 ,  H01L23/538 ,  H01L23/31

CPC classification number: H01L24/17 ,  H01L24/13 ,  H01L23/5384 ,  H01L23/3135 ,  H01L2224/13009 ,  H01L2224/13023 ,  H01L2224/13008

Abstract: A semiconductor package includes a lower redistribution layer including an insulating pattern having an opening and a via in the opening; a first semiconductor chip including a chip pad, a passivation layer, and a pad bump connected to the chip pad; and a first encapsulant on the lower redistribution layer and the first semiconductor chip. The opening defines a lower surface and a side surface of the pad bump, and the via is in physical contact with the lower surface and the side surface of the pad bump.

公开(公告)号：US11373955B2

公开(公告)日：2022-06-28

申请号：US17032210

申请日：2020-09-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Changeun Joo ,  Gyujin Choi

IPC: H01L23/538 ,  H01L23/498 ,  H01L21/56

Abstract: A semiconductor package includes a core substrate having a through hole, a first molding member at least partially filling the through hole and covering an upper surface of the core substrate, the first molding member having a cavity within the through hole, a first semiconductor chip on the first molding member on the upper surface of the core substrate, a second semiconductor chip arranged within the cavity, a second molding member on the first molding member and covering the first semiconductor chip, a third molding member filling the cavity and covering the lower surface of the core substrate; first redistribution wirings on the second molding member and electrically connecting first chip pads of the first semiconductor chip and core connection wirings of the core substrate; and second redistribution wirings on the third molding member and electrically connecting second chip pads of the second semiconductor chip and the core connection wirings.