公开(公告)号：US20230178440A1

公开(公告)日：2023-06-08

申请号：US17677329

申请日：2022-02-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： MING HE ,  Jaehyun Park ,  Mehdi Saremi ,  Rebecca Park ,  Harsono Simka ,  Daewon Ha

IPC: H01L21/8238 ,  H01L27/092

CPC classification number: H01L21/823814 ,  H01L27/0922 ,  H01L21/823871 ,  H01L21/823878 ,  H01L29/0665

Abstract: Integrated circuit devices and methods of forming the integrated circuit device are provided. The methods may include providing a preliminary transistor stack including an upper sacrificial layer on a substrate, an upper active region between the substrate and the upper sacrificial layer, a lower sacrificial layer between the substrate and the upper active region, and a lower active region between the substrate and the lower sacrificial layer. The methods may further include forming lower source/drain regions on respective opposing side surfaces of the lower active region, forming a preliminary capping layer on a first lower source/drain region of the lower source/drain regions, the preliminary capping layer including a semiconductor material, converting the preliminary capping layer to a capping layer that includes an insulating material, and forming upper source/drain regions on respective opposing side surfaces of the upper active region.

公开(公告)号：US20230178420A1

公开(公告)日：2023-06-08

申请号：US17679465

申请日：2022-02-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ming He ,  JaeHyun Park ,  Chihak Ahn ,  Mehdi Saremi ,  Rebecca Park ,  Harsono Simka ,  Daewon Ha

IPC: H01L21/762 ,  H01L29/423 ,  H01L29/786 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L21/76283 ,  H01L29/42392 ,  H01L29/78696 ,  H01L29/0665 ,  H01L29/6653

Abstract: Methods of forming transistor devices are provided. A method of forming a transistor device includes providing a nanosheet stack that includes a plurality of nanosheets on a substrate. A sacrificial layer is between the nanosheet stack and the substrate. The method includes removing the sacrificial layer to form an opening between the nanosheet stack and the substrate. The method includes forming a gate spacer and an isolation region by forming an insulating material on the nanosheet stack and in the opening, respectively. Related transistor devices are also provided.

公开(公告)号：US11289419B2

公开(公告)日：2022-03-29

申请号：US16942392

申请日：2020-07-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jorge A. Kittl ,  Ganesh Hegde ,  Harsono Simka

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532

Abstract: A method of manufacturing metallic interconnects for an integrated circuit includes forming an interconnect layout including at least one line including a non-diffusing material, forming a diffusing barrier layer on the line, forming an opening extending completely through the diffusing barrier layer and exposing a portion of the line, depositing a diffusing layer on the diffusing barrier layer such that a portion of the diffusing layer contacts the portion of the line, and thermally reacting the diffusing layer to form the metallic interconnects. Thermally reacting the diffusing layer chemically diffuses a material of the diffusing layer into the at least one line and causes at least one crystalline grain to grow along a length of the at least one line from at least one nucleation site defined at an interface between the portions of the diffusing layer and the line.

公开(公告)号：US10763207B2

公开(公告)日：2020-09-01

申请号：US15939211

申请日：2018-03-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jorge A. Kittl ,  Ganesh Hegde ,  Harsono Simka

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532

Abstract: A method of manufacturing metallic interconnects for an integrated circuit includes forming an interconnect layout including at least one line including a non-diffusing material, forming a diffusing barrier layer on the line, forming an opening extending completely through the diffusing barrier layer and exposing a portion of the line, depositing a diffusing layer on the diffusing barrier layer such that a portion of the diffusing layer contacts the portion of the line, and thermally reacting the diffusing layer to form the metallic interconnects. Thermally reacting the diffusing layer chemically diffuses a material of the diffusing layer into the at least one line and causes at least one crystalline grain to grow along a length of the at least one line from at least one nucleation site defined at an interface between the portions of the diffusing layer and the line.

公开(公告)号：US20250072098A1

公开(公告)日：2025-02-27

申请号：US18486884

申请日：2023-10-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Mehdi Saremi ,  Ming He ,  Aravindh Kumar ,  Muhammed Ahosan Ul Karim ,  Rebecca Park ,  Harsono Simka

IPC: H01L21/8238 ,  H01L29/08

Abstract: A method of manufacturing a three-dimensional field-effect transistor including an upper field-effect transistor stacked on a lower field-effect transistor. The method includes epitaxially growing source/drain regions of the lower field-effect effect transistor, growing a sacrificial layer on an upper surface of the source/drain regions, and epitaxially growing source/drain regions of the upper field-effect transistor on the sacrificial layer. The sacrificial layer is a seed layer for the source/drain regions of the upper field-effect transistor. The method also includes selectively etching the sacrificial layer to form a gap between the source/drain regions of the lower field-effect transistor and the source/drain regions of the upper field-effect transistor, and depositing an oxide layer in the gap.

公开(公告)号：US20240047539A1

公开(公告)日：2024-02-08

申请号：US17984025

申请日：2022-11-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ming He ,  Mehdi Saremi ,  Rebecca Park ,  Muhammed Ahosan Ul Karim ,  Harsono Simka ,  Sungil Park ,  Myungil Kang ,  Kyungho Kim ,  Doyoung Choi ,  JaeHyun Park

IPC: H01L29/417 ,  H01L29/10 ,  H01L29/20 ,  H01L29/66 ,  H01L29/808

CPC classification number: H01L29/41791 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/6681 ,  H01L29/8083

Abstract: Provided is a three-dimensionally stacked field-effect transistor (3DSFET) device which includes: a lower source/drain region of a 1st polarity type connected to a lower channel structure; an upper source/drain region of a 2nd polarity type, connected to an upper channel structure, above the lower source/drain region; and a PN junction structure, between the lower source/drain region and the upper source/drain region, configured to electrically isolate the upper source/drain region from the lower source/drain region, wherein the PN junction structure includes a 1st region of the 1st polarity type and a 2nd region of the 2nd polarity type.

公开(公告)号：US20190157200A1

公开(公告)日：2019-05-23

申请号：US15939211

申请日：2018-03-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jorge A. Kittl ,  Ganesh Hegde ,  Harsono Simka

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/532 ,  H01L23/528

Abstract: A method of manufacturing metallic interconnects for an integrated circuit includes forming an interconnect layout including at least one line including a non-diffusing material, forming a diffusing barrier layer on the line, forming an opening extending completely through the diffusing barrier layer and exposing a portion of the line, depositing a diffusing layer on the diffusing barrier layer such that a portion of the diffusing layer contacts the portion of the line, and thermally reacting the diffusing layer to form the metallic interconnects. Thermally reacting the diffusing layer chemically diffuses a material of the diffusing layer into the at least one line and causes at least one crystalline grain to grow along a length of the at least one line from at least one nucleation site defined at an interface between the portions of the diffusing layer and the line.