公开(公告)号：US10734493B2

公开(公告)日：2020-08-04

申请号：US16029993

申请日：2018-07-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hauk Han ,  Je-hyeon Park ,  Do-hyung Kim ,  Tae-yong Kim ,  Keun Lee ,  Jeong-gil Lee ,  Hyun-seok Lim

IPC: H01L29/423 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78 ,  H01L29/49 ,  H01L27/11582 ,  H01L27/1157 ,  H01L29/786

Abstract: A semiconductor memory device may include a substrate, gate electrode structures stacked on the substrate, insulation patterns between the gate electrode structures, vertical channels penetrating through the gate electrode structures and the insulation patterns, and a data storage pattern. The vertical channels may be electrically connected to the substrate. The data storage pattern may be arranged between the gate electrode structures and the vertical channels. Each of the gate electrode structures may include a barrier film, a metal gate, and a crystal grain boundary plugging layer. The crystal grain boundary plugging layer may be between the barrier film and the metal gate.

公开(公告)号：US08928092B2

公开(公告)日：2015-01-06

申请号：US13940721

申请日：2013-07-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hauk Han ,  Yong-Il Kwon ,  JungSuk Oh ,  Tae sun Ryu ,  Jeonggil Lee

IPC: H01L27/088 ,  H01L29/788 ,  H01L23/52 ,  H01L21/28 ,  H01L27/115

CPC classification number: H01L27/11531 ,  H01L21/28273 ,  H01L23/52 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11536 ,  H01L27/11539 ,  H01L29/42328 ,  H01L29/4238 ,  H01L29/4941 ,  H01L29/788 ,  H01L29/7881 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a lower insulating pattern on a semiconductor substrate, a lower gate pattern on the lower insulating pattern and formed of a doped polysilicon layer, a residual insulating pattern with an opening exposing a portion of a top surface of the lower gate pattern, an upper gate pattern on the residual insulating pattern, the upper gate pattern filling the opening, and a diffusion barrier pattern in contact with the portion of the top surface of the lower gate pattern and extending between the residual insulating pattern and the upper gate pattern.

Abstract translation: 半导体器件包括在半导体衬底上的下绝缘图案，下绝缘图案上的下栅极图案和由掺杂多晶硅层形成的残留绝缘图案，具有露出下栅极图案的顶表面的一部分的开口， 剩余绝缘图案上的上栅极图案，填充开口的上栅极图案，以及与下栅极图案的顶表面的部分接触并在残留绝缘图案和上栅极图案之间延伸的扩散阻挡图案。

公开(公告)号：US20250081462A1

公开(公告)日：2025-03-06

申请号：US18952236

申请日：2024-11-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hauk Han ,  Taeyong Kim ,  Keun Lee ,  Jeonggil Lee ,  Taisoo Lim ,  Hanmei Choi

IPC: H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10

Abstract: A semiconductor device includes gate electrodes stacked and spaced apart from each other in a first direction perpendicular to an upper surface of a substrate; interlayer insulating layers alternately stacked with the gate electrodes on the substrate; channel structures extending through the gate electrodes; and a separation region extending through the gate electrodes in the first direction and extending in a second direction perpendicular to the first direction, wherein each of the gate electrodes comprises a first conductive layer and a second conductive layer sequentially stacked, the second conductive layer including a metal nitride, and wherein the first conductive layer and the second conductive layer are each in physical contact with the separation region.

公开(公告)号：US11744073B2

公开(公告)日：2023-08-29

申请号：US17530915

申请日：2021-11-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taisoo Lim ,  Kyungwook Park ,  Keun Lee ,  Hauk Han

IPC: H10B43/27 ,  H10B43/10 ,  H10B43/40 ,  H01L29/423 ,  H01L21/67 ,  H01L21/285 ,  H01L21/3213 ,  C23C16/56 ,  C23C16/455 ,  C23C16/06 ,  H01L21/28 ,  H01L21/02 ,  H01L29/66

CPC classification number: H10B43/27 ,  C23C16/06 ,  C23C16/45525 ,  C23C16/56 ,  H01L21/28568 ,  H01L21/32135 ,  H01L21/67069 ,  H01L29/40117 ,  H01L29/4234 ,  H10B43/10 ,  H10B43/40 ,  H01L21/02636 ,  H01L21/67167 ,  H01L29/66545

Abstract: A semiconductor device includes gate electrodes and interlayer insulating layers that are alternately stacked on a substrate, channel structures spaced apart from each other in a first direction and extending vertically through the gate electrodes and the interlayer insulating layers to the substrate, and a first separation region extending vertically through the gate electrodes and the interlayer insulating layers. Each gate electrode includes a first conductive layer and a second conductive layer, the first conductive layer disposed between the second conductive layer and each of two adjacent interlayer insulating layers. In a first region, between an outermost channel structure and the first separation region, of each gate electrode, the first conductive layer has a decreasing thickness toward the first separation region and the second conductive layer has an increasing thickness toward the first separation region.

公开(公告)号：US20190013388A1

公开(公告)日：2019-01-10

申请号：US16029993

申请日：2018-07-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hauk Han ,  Je-Hyeon Park ,  Do-hyung Kim ,  Tae-yong Kim ,  Keun Lee ,  Jeong-gil Lee ,  Hyun-seok Lim

IPC: H01L29/423 ,  H01L29/51 ,  H01L29/66 ,  H01L29/49 ,  H01L29/78

Abstract: A semiconductor memory device may include a substrate, gate electrode structures stacked on the substrate, insulation patterns between the gate electrode structures, vertical channels penetrating through the gate electrode structures and the insulation patterns, and a data storage pattern. The vertical channels may be electrically connected to the substrate. The data storage pattern may be arranged between the gate electrode structures and the vertical channels. Each of the gate electrode structures may include a barrier film, a metal gate, and a crystal grain boundary plugging layer. The crystal grain boundary plugging layer may be between the barrier film and the metal gate.

公开(公告)号：US09245899B2

公开(公告)日：2016-01-26

申请号：US14740476

申请日：2015-06-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hauk Han ,  Yong-IL Kwon ,  JungSuk Oh ,  Tae sun Ryu ,  Jeonggil Lee

IPC: H01L27/115 ,  H01L29/423 ,  H01L29/49

CPC classification number: H01L27/11531 ,  H01L21/28273 ,  H01L23/52 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11536 ,  H01L27/11539 ,  H01L29/42328 ,  H01L29/4238 ,  H01L29/4941 ,  H01L29/788 ,  H01L29/7881 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a lower insulating pattern on a semiconductor substrate, a lower gate pattern on the lower insulating pattern and formed of a doped polysilicon layer, a residual insulating pattern with an opening exposing a portion of a top surface of the lower gate pattern, an upper gate pattern on the residual insulating pattern, the upper gate pattern filling the opening, and a diffusion barrier pattern in contact with the portion of the top surface of the lower gate pattern and extending between the residual insulating pattern and the upper gate pattern.

公开(公告)号：US20150084109A1

公开(公告)日：2015-03-26

申请号：US14561788

申请日：2014-12-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hauk Han ,  Yong-IL Kwon ,  JungSuk Oh ,  Tae sun Ryu ,  Jeonggil Lee

IPC: H01L27/115 ,  H01L29/423 ,  H01L29/49

CPC classification number: H01L27/11531 ,  H01L21/28273 ,  H01L23/52 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11536 ,  H01L27/11539 ,  H01L29/42328 ,  H01L29/4238 ,  H01L29/4941 ,  H01L29/788 ,  H01L29/7881 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a lower insulating pattern on a semiconductor substrate, a lower gate pattern on the lower insulating pattern and formed of a doped polysilicon layer, a residual insulating pattern with an opening exposing a portion of a top surface of the lower gate pattern, an upper gate pattern on the residual insulating pattern, the upper gate pattern filling the opening, and a diffusion barrier pattern in contact with the portion of the top surface of the lower gate pattern and extending between the residual insulating pattern and the upper gate pattern.

Abstract translation: 半导体器件包括在半导体衬底上的下绝缘图案，下绝缘图案上的下栅极图案和由掺杂多晶硅层形成的残留绝缘图案，具有露出下栅极图案的顶表面的一部分的开口， 剩余绝缘图案上的上栅极图案，填充开口的上栅极图案，以及与下栅极图案的顶表面的部分接触并在残留绝缘图案和上栅极图案之间延伸的扩散阻挡图案。