公开(公告)号：US20250081462A1

公开(公告)日：2025-03-06

申请号：US18952236

申请日：2024-11-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hauk Han ,  Taeyong Kim ,  Keun Lee ,  Jeonggil Lee ,  Taisoo Lim ,  Hanmei Choi

IPC: H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10

Abstract: A semiconductor device includes gate electrodes stacked and spaced apart from each other in a first direction perpendicular to an upper surface of a substrate; interlayer insulating layers alternately stacked with the gate electrodes on the substrate; channel structures extending through the gate electrodes; and a separation region extending through the gate electrodes in the first direction and extending in a second direction perpendicular to the first direction, wherein each of the gate electrodes comprises a first conductive layer and a second conductive layer sequentially stacked, the second conductive layer including a metal nitride, and wherein the first conductive layer and the second conductive layer are each in physical contact with the separation region.

公开(公告)号：US11744073B2

公开(公告)日：2023-08-29

申请号：US17530915

申请日：2021-11-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taisoo Lim ,  Kyungwook Park ,  Keun Lee ,  Hauk Han

IPC: H10B43/27 ,  H10B43/10 ,  H10B43/40 ,  H01L29/423 ,  H01L21/67 ,  H01L21/285 ,  H01L21/3213 ,  C23C16/56 ,  C23C16/455 ,  C23C16/06 ,  H01L21/28 ,  H01L21/02 ,  H01L29/66

CPC classification number: H10B43/27 ,  C23C16/06 ,  C23C16/45525 ,  C23C16/56 ,  H01L21/28568 ,  H01L21/32135 ,  H01L21/67069 ,  H01L29/40117 ,  H01L29/4234 ,  H10B43/10 ,  H10B43/40 ,  H01L21/02636 ,  H01L21/67167 ,  H01L29/66545

Abstract: A semiconductor device includes gate electrodes and interlayer insulating layers that are alternately stacked on a substrate, channel structures spaced apart from each other in a first direction and extending vertically through the gate electrodes and the interlayer insulating layers to the substrate, and a first separation region extending vertically through the gate electrodes and the interlayer insulating layers. Each gate electrode includes a first conductive layer and a second conductive layer, the first conductive layer disposed between the second conductive layer and each of two adjacent interlayer insulating layers. In a first region, between an outermost channel structure and the first separation region, of each gate electrode, the first conductive layer has a decreasing thickness toward the first separation region and the second conductive layer has an increasing thickness toward the first separation region.

公开(公告)号：US20210384217A1

公开(公告)日：2021-12-09

申请号：US17151383

申请日：2021-01-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hauk Han ,  Taeyong Kim ,  Keun Lee ,  Jeonggil Lee ,  Taisoo Lim ,  Hanmei Choi

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/11519 ,  H01L27/11556

Abstract: A semiconductor device includes gate electrodes stacked and spaced apart from each other in a first direction perpendicular to an upper surface of a substrate; interlayer insulating layers alternately stacked with the gate electrodes on the substrate; channel structures extending through the gate electrodes; and a separation region extending through the gate electrodes in the first direction and extending in a second direction perpendicular to the first direction, wherein each of the gate electrodes comprises a first conductive layer and a second conductive layer sequentially stacked, the second conductive layer including a metal nitride, and wherein the first conductive layer and the second conductive layer are each in physical contact with the separation region.

公开(公告)号：US20200303409A1

公开(公告)日：2020-09-24

申请号：US16700801

申请日：2019-12-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taisoo Lim ,  Kyungwook Park ,  Keun Lee ,  Hauk Han

IPC: H01L27/11582 ,  H01L29/423 ,  H01L21/67 ,  H01L27/11565 ,  H01L27/11573 ,  H01L21/285 ,  H01L21/28 ,  H01L21/3213 ,  C23C16/56 ,  C23C16/455 ,  C23C16/06

Abstract: A semiconductor device includes gate electrodes and interlayer insulating layers that are alternately stacked on a substrate, channel structures spaced apart from each other in a first direction and extending vertically through the gate electrodes and the interlayer insulating layers to the substrate, and a first separation region extending vertically through the gate electrodes and the interlayer insulating layers. Each gate electrode includes a first conductive layer and a second conductive layer, the first conductive layer disposed between the second conductive layer and each of two adjacent interlayer insulating layers. In a first region, between an outermost channel structure and the first separation region, of each gate electrode, the first conductive layer has a decreasing thickness toward the first separation region and the second conductive layer has an increasing thickness toward the first separation region.

公开(公告)号：US11770929B2

公开(公告)日：2023-09-26

申请号：US16993345

申请日：2020-08-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sunil Shim ,  Suhyeong Lee ,  Taisoo Lim

IPC: H10B43/27 ,  H01L21/28 ,  H01L29/423 ,  H10B41/27 ,  H10B41/35 ,  H10B43/35

CPC classification number: H10B43/27 ,  H01L29/40114 ,  H01L29/40117 ,  H01L29/4234 ,  H01L29/42324 ,  H10B41/27 ,  H10B41/35 ,  H10B43/35

Abstract: A semiconductor device includes gate layers stacked on a substrate in a first direction perpendicular to an upper surface of the substrate, and channel structures penetrating the gate layers and extending in the first direction, each of the channel structures includes first dielectric layers on side surfaces of the gate layers, respectively, and spaced apart from each other in the first direction, electric charge storage layers on side surfaces of the first dielectric layers, respectively, and spaced apart from each other in the first direction, a second dielectric layer extending perpendicularly to the substrate to conform to side surfaces of the electric change storage layers, and a channel layer extending perpendicularly, and each of the first dielectric layers has a first maximum length, and each of the electric charge storage layers has a second maximum length greater than the first maximum length in the first direction.

公开(公告)号：US20220077190A1

公开(公告)日：2022-03-10

申请号：US17530915

申请日：2021-11-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taisoo Lim ,  Kyungwook Park ,  Keun Lee ,  Hauk Han

IPC: H01L27/11582 ,  H01L29/423 ,  H01L21/67 ,  H01L27/11565 ,  H01L27/11573 ,  H01L21/285 ,  H01L21/3213 ,  C23C16/56 ,  C23C16/455 ,  C23C16/06 ,  H01L21/28

Abstract: A semiconductor device includes gate electrodes and interlayer insulating layers that are alternately stacked on a substrate, channel structures spaced apart from each other in a first direction and extending vertically through the gate electrodes and the interlayer insulating layers to the substrate, and a first separation region extending vertically through the gate electrodes and the interlayer insulating layers. Each gate electrode includes a first conductive layer and a second conductive layer, the first conductive layer disposed between the second conductive layer and each of two adjacent interlayer insulating layers. In a first region, between an outermost channel structure and the first separation region, of each gate electrode, the first conductive layer has a decreasing thickness toward the first separation region and the second conductive layer has an increasing thickness toward the first separation region.

公开(公告)号：US20210066346A1

公开(公告)日：2021-03-04

申请号：US16854189

申请日：2020-04-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taisoo Lim ,  Suhyeong Lee

IPC: H01L27/11582 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792

Abstract: Semiconductor devices are provided. A semiconductor device includes gate electrodes on a substrate and stacked perpendicularly to an upper surface of the substrate. The semiconductor device includes interlayer insulating layers alternately stacked with the gate electrodes. Moreover, the semiconductor device includes channel structures passing through the gate electrodes. Each of the channel structures includes a channel layer extending perpendicularly to the upper surface of the substrate, a tunneling insulating layer on the channel layer, charge storage layers on the tunneling insulating layer in respective regions between the gate electrodes and a side surface of the tunneling insulating layer, and first blocking insulating layers on the charge storage layers, respectively. A first layer of the first blocking insulating layers is on an upper surface, a lower surface, and a side surface of a first layer of the charge storage layers.

公开(公告)号：US20240237351A1

公开(公告)日：2024-07-11

申请号：US18581049

申请日：2024-02-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taisoo Lim ,  Suhyeong Lee

IPC: H10B43/27 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/35

CPC classification number: H10B43/27 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/7889 ,  H01L29/7926 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/35

Abstract: Semiconductor devices are provided. A semiconductor device includes gate electrodes on a substrate and stacked perpendicularly to an upper surface of the substrate. The semiconductor device includes interlayer insulating layers alternately stacked with the gate electrodes. Moreover, the semiconductor device includes channel structures passing through the gate electrodes. Each of the channel structures includes a channel layer extending perpendicularly to the upper surface of the substrate, a tunneling insulating layer on the channel layer, charge storage layers on the tunneling insulating layer in respective regions between the gate electrodes and a side surface of the tunneling insulating layer, and first blocking insulating layers on the charge storage layers, respectively. A first layer of the first blocking insulating layers is on an upper surface, a lower surface, and a side surface of a first layer of the charge storage layers.

公开(公告)号：US11937425B2

公开(公告)日：2024-03-19

申请号：US16854189

申请日：2020-04-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taisoo Lim ,  Suhyeong Lee

IPC: H10B43/27 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/35

CPC classification number: H10B43/27 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/7889 ,  H01L29/7926 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/35

Abstract: Semiconductor devices are provided. A semiconductor device includes gate electrodes on a substrate and stacked perpendicularly to an upper surface of the substrate. The semiconductor device includes interlayer insulating layers alternately stacked with the gate electrodes. Moreover, the semiconductor device includes channel structures passing through the gate electrodes. Each of the channel structures includes a channel layer extending perpendicularly to the upper surface of the substrate, a tunneling insulating layer on the channel layer, charge storage layers on the tunneling insulating layer in respective regions between the gate electrodes and a side surface of the tunneling insulating layer, and first blocking insulating layers on the charge storage layers, respectively. A first layer of the first blocking insulating layers is on an upper surface, a lower surface, and a side surface of a first layer of the charge storage layers.

公开(公告)号：US11930641B2

公开(公告)日：2024-03-12

申请号：US17206277

申请日：2021-03-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jeonggil Lee ,  Taisoo Lim ,  Hauk Han

IPC: H10B43/50 ,  H01L21/768 ,  H01L23/535 ,  H10B41/27 ,  H10B41/41 ,  H10B41/50 ,  H10B43/27 ,  H10B43/40

CPC classification number: H10B43/50 ,  H01L21/76805 ,  H01L21/76895 ,  H01L23/535 ,  H10B41/27 ,  H10B41/41 ,  H10B41/50 ,  H10B43/27 ,  H10B43/40

Abstract: A semiconductor device includes circuit elements on a first substrate; gate electrodes on a second substrate and stacked to be apart from each other in a first direction; sacrificial insulating layers on a lower through-insulating layer penetrating the second substrate, stacked to be spaced apart from each other in the first direction, and having side surfaces opposing the gate electrodes; channel structures penetrating the gate electrodes, extending vertically on the second substrate, and including a channel layer; a first separation pattern penetrating the gate electrodes and including a first barrier pattern and a first pattern portion extending from the first barrier pattern in a second direction; and a second separation pattern penetrating the gate electrodes, disposed to be parallel to the first separation pattern, and extending in the second direction. Some of the side surfaces of the sacrificial insulating layers may overlap the first barrier pattern in a third direction.