公开(公告)号：US11930641B2

公开(公告)日：2024-03-12

申请号：US17206277

申请日：2021-03-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jeonggil Lee ,  Taisoo Lim ,  Hauk Han

IPC: H10B43/50 ,  H01L21/768 ,  H01L23/535 ,  H10B41/27 ,  H10B41/41 ,  H10B41/50 ,  H10B43/27 ,  H10B43/40

CPC classification number: H10B43/50 ,  H01L21/76805 ,  H01L21/76895 ,  H01L23/535 ,  H10B41/27 ,  H10B41/41 ,  H10B41/50 ,  H10B43/27 ,  H10B43/40

Abstract: A semiconductor device includes circuit elements on a first substrate; gate electrodes on a second substrate and stacked to be apart from each other in a first direction; sacrificial insulating layers on a lower through-insulating layer penetrating the second substrate, stacked to be spaced apart from each other in the first direction, and having side surfaces opposing the gate electrodes; channel structures penetrating the gate electrodes, extending vertically on the second substrate, and including a channel layer; a first separation pattern penetrating the gate electrodes and including a first barrier pattern and a first pattern portion extending from the first barrier pattern in a second direction; and a second separation pattern penetrating the gate electrodes, disposed to be parallel to the first separation pattern, and extending in the second direction. Some of the side surfaces of the sacrificial insulating layers may overlap the first barrier pattern in a third direction.

公开(公告)号：US09721967B2

公开(公告)日：2017-08-01

申请号：US15138873

申请日：2016-04-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sunwoo Lee ,  Sangwoo Lee ,  Changwon Lee ,  Jeonggil Lee

IPC: H01L27/115 ,  H01L27/11582 ,  H01L21/28 ,  H01L27/11578 ,  H01L29/49 ,  H01L23/535 ,  H01L27/1157

CPC classification number: H01L27/11582 ,  H01L21/28282 ,  H01L23/535 ,  H01L27/1157 ,  H01L27/11578 ,  H01L27/1159 ,  H01L29/4958 ,  H01L29/4966

Abstract: A nonvolatile memory device includes gate electrodes three dimensionally arranged on a semiconductor substrate, a semiconductor pattern extending from the semiconductor substrate and crossing sidewalls of the gate electrodes, a metal liner pattern formed between the semiconductor pattern and formed on a top surface and a bottom surface of each of the gate electrodes, and a charge storage layer formed between the semiconductor pattern and the metal liner pattern.

公开(公告)号：US08928092B2

公开(公告)日：2015-01-06

申请号：US13940721

申请日：2013-07-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hauk Han ,  Yong-Il Kwon ,  JungSuk Oh ,  Tae sun Ryu ,  Jeonggil Lee

IPC: H01L27/088 ,  H01L29/788 ,  H01L23/52 ,  H01L21/28 ,  H01L27/115

CPC classification number: H01L27/11531 ,  H01L21/28273 ,  H01L23/52 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11536 ,  H01L27/11539 ,  H01L29/42328 ,  H01L29/4238 ,  H01L29/4941 ,  H01L29/788 ,  H01L29/7881 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a lower insulating pattern on a semiconductor substrate, a lower gate pattern on the lower insulating pattern and formed of a doped polysilicon layer, a residual insulating pattern with an opening exposing a portion of a top surface of the lower gate pattern, an upper gate pattern on the residual insulating pattern, the upper gate pattern filling the opening, and a diffusion barrier pattern in contact with the portion of the top surface of the lower gate pattern and extending between the residual insulating pattern and the upper gate pattern.

Abstract translation: 半导体器件包括在半导体衬底上的下绝缘图案，下绝缘图案上的下栅极图案和由掺杂多晶硅层形成的残留绝缘图案，具有露出下栅极图案的顶表面的一部分的开口， 剩余绝缘图案上的上栅极图案，填充开口的上栅极图案，以及与下栅极图案的顶表面的部分接触并在残留绝缘图案和上栅极图案之间延伸的扩散阻挡图案。

公开(公告)号：US11462553B2

公开(公告)日：2022-10-04

申请号：US17034274

申请日：2020-09-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Shinjae Kang ,  Woosung Lee ,  Jeonggil Lee ,  Hanmei Choi ,  Hauk Han

IPC: H01L27/11556 ,  H01L27/11519 ,  H01L27/11526 ,  H01L23/522 ,  H01L27/11573 ,  H01L27/11582 ,  H01L27/11565

Abstract: Semiconductor devices including a substrate including a cell array region and a through electrode region, an electrode stack on the substrate and including electrodes, vertical structures penetrating the electrode stack within the cell array region, vertical fence structures within an extension region and surrounding the through electrode region, and insulating layers being inside a perimeter defined by the vertical fence structures and being at the same level as the electrodes may be provided. The electrodes may include first protrusions protruding between the vertical fence structures in a plan view.

公开(公告)号：US20210225767A1

公开(公告)日：2021-07-22

申请号：US17029183

申请日：2020-09-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeonggil Lee ,  Sukhoon Kim ,  Sungmyong Park ,  Chanyang Lee ,  Honyun Park

IPC: H01L23/528

Abstract: A wiring structure includes first to third metal patterns on a substrate. The first metal pattern extends in a second direction and has a first width in a third direction. The second metal pattern extends in the third direction to cross the first metal pattern and have a second width in the second direction. The third metal pattern is connected to the first and second metal patterns at an area where the first and second metal patterns cross each other, and has a substantially rectangular shape with concave portions in each quadrant. The third metal pattern has a third width defined as a minimum distance between opposite ones of the concave portions in a fourth direction having an acute angle to the second and third directions, which is less or equal to than a smaller of the first and second widths.

公开(公告)号：US10347527B2

公开(公告)日：2019-07-09

申请号：US15975003

申请日：2018-05-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sangho Rha ,  Kyoung Hee Nam ,  Jeonggil Lee ,  Hyunseok Lim ,  Seungjong Park ,  Seulgi Bae ,  Jaejin Lee ,  Kwangtae Hwang

IPC: H01L21/768 ,  H01L23/532

Abstract: A semiconductor device includes a substrate, a first metal interconnection provided on a first region of the substrate, and a second metal interconnection provided on a second region of the substrate. A width of the second metal interconnection is greater than a width of the first metal interconnection. The first metal interconnection includes a metal pattern. The second metal interconnection includes a lower metal pattern having a concave surface at its top, an upper metal pattern disposed on the concave surface at the top of the lower metal pattern, and a first barrier pattern interposed between the lower metal pattern and the upper metal pattern. The metal interconnections are formed by a damascene process including deposition, reflow, metal implantation, and planarization processes.

公开(公告)号：US20150311298A1

公开(公告)日：2015-10-29

申请号：US14740476

申请日：2015-06-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hauk Han ,  Yong-IL Kwon ,  JungSuk Oh ,  Tae sun Ryu ,  Jeonggil Lee

IPC: H01L29/423 ,  H01L29/49 ,  H01L27/115

CPC classification number: H01L27/11531 ,  H01L21/28273 ,  H01L23/52 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11536 ,  H01L27/11539 ,  H01L29/42328 ,  H01L29/4238 ,  H01L29/4941 ,  H01L29/788 ,  H01L29/7881 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a lower insulating pattern on a semiconductor substrate, a lower gate pattern on the lower insulating pattern and formed of a doped polysilicon layer, a residual insulating pattern with an opening exposing a portion of a top surface of the lower gate pattern, an upper gate pattern on the residual insulating pattern, the upper gate pattern filling the opening, and a diffusion barrier pattern in contact with the portion of the top surface of the lower gate pattern and extending between the residual insulating pattern and the upper gate pattern.

公开(公告)号：US20210384217A1

公开(公告)日：2021-12-09

申请号：US17151383

申请日：2021-01-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hauk Han ,  Taeyong Kim ,  Keun Lee ,  Jeonggil Lee ,  Taisoo Lim ,  Hanmei Choi

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/11519 ,  H01L27/11556

Abstract: A semiconductor device includes gate electrodes stacked and spaced apart from each other in a first direction perpendicular to an upper surface of a substrate; interlayer insulating layers alternately stacked with the gate electrodes on the substrate; channel structures extending through the gate electrodes; and a separation region extending through the gate electrodes in the first direction and extending in a second direction perpendicular to the first direction, wherein each of the gate electrodes comprises a first conductive layer and a second conductive layer sequentially stacked, the second conductive layer including a metal nitride, and wherein the first conductive layer and the second conductive layer are each in physical contact with the separation region.

公开(公告)号：US09343478B2

公开(公告)日：2016-05-17

申请号：US14486547

申请日：2014-09-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SunWoo Lee ,  Sangwoo Lee ,  Changwon Lee ,  Jeonggil Lee

IPC: H01L27/115 ,  H01L21/28 ,  H01L29/49

CPC classification number: H01L27/11582 ,  H01L21/28282 ,  H01L23/535 ,  H01L27/1157 ,  H01L27/11578 ,  H01L27/1159 ,  H01L29/4958 ,  H01L29/4966

Abstract: A nonvolatile memory device includes gate electrodes three dimensionally arranged on a semiconductor substrate, a semiconductor pattern extending from the semiconductor substrate and crossing sidewalls of the gate electrodes, a metal liner pattern formed between the semiconductor pattern and formed on a top surface and a bottom surface of each of the gate electrodes, and a charge storage layer formed between the semiconductor pattern and the metal liner pattern.

Abstract translation: 非易失性存储器件包括三维地布置在半导体衬底上的栅电极，从半导体衬底延伸并与栅电极的侧壁交叉的半导体图案，形成在半导体图案之间并形成在顶表面和底表面上的金属衬垫图案 以及形成在半导体图案和金属衬垫图案之间的电荷存储层。

公开(公告)号：US08865579B2

公开(公告)日：2014-10-21

申请号：US13667618

申请日：2012-11-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sunwoo Lee ,  Sangwoo Lee ,  Changwon Lee ,  Jeonggil Lee

IPC: H01L29/72 ,  H01L27/115 ,  H01L21/28

CPC classification number: H01L27/11582 ,  H01L21/28282 ,  H01L23/535 ,  H01L27/1157 ,  H01L27/11578 ,  H01L27/1159 ,  H01L29/4958 ,  H01L29/4966

Abstract: A nonvolatile memory device includes gate electrodes three dimensionally arranged on a semiconductor substrate, a semiconductor pattern extending from the semiconductor substrate and crossing sidewalls of the gate electrodes, a metal liner pattern formed between the semiconductor pattern and formed on a top surface and a bottom surface of each of the gate electrodes, and a charge storage layer formed between the semiconductor pattern and the metal liner pattern.

Abstract translation: 非易失性存储器件包括三维地布置在半导体衬底上的栅电极，从半导体衬底延伸并与栅电极的侧壁交叉的半导体图案，形成在半导体图案之间并形成在顶表面和底表面上的金属衬垫图案 以及形成在半导体图案和金属衬垫图案之间的电荷存储层。