公开(公告)号：US20230361121A1

公开(公告)日：2023-11-09

申请号：US18353214

申请日：2023-07-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongsoo LEE ,  Wonkeun CHUNG ,  Hoonjoo NA ,  Suyoung BAE ,  Jaeyeol SONG ,  Jonghan LEE ,  HyungSuk JUNG ,  Sangjin HYUN

IPC: H01L27/092 ,  H01L29/786 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/51 ,  H01L29/423

CPC classification number: H01L27/0922 ,  H01L29/78696 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/42392

Abstract: Disclosed are semiconductor devices and methods of manufacturing the same. The semiconductor device comprises a first transistor on a substrate, and a second transistor on the substrate. Each of the first and second transistors includes a plurality of semiconductor patterns vertically stacked on the substrate and vertically spaced apart from each other, and a gate dielectric pattern and a work function pattern filling a space between the semiconductor patterns. The work function pattern of the first transistor includes a first work function metal layer, the work function pattern of the second transistor includes the first work function metal layer and a second work function metal layer, the first work function metal layer of each of the first and second transistors has a work function greater than that of the second work function metal layer, and the first transistor has a threshold voltage less than that of the second transistor.

公开(公告)号：US20220310541A1

公开(公告)日：2022-09-29

申请号：US17541719

申请日：2021-12-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hoonjoo NA ,  Jungseob SO ,  Taeseong KIM ,  Sohye CHO ,  Sonkwan HWANG

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18

Abstract: The semiconductor device includes a lower chip structure including a peripheral circuit, a first memory chip structure on the lower chip structure, and a second memory chip structure on the first memory chip structure. The first memory chip structure includes a first stack structure and a first vertical memory structure. The first stack structure includes first gate lines stacked in a vertical direction and extending in a first horizontal direction. The first vertical memory structure penetrates through the first gate lines in the vertical direction. The second memory chip structure includes a second stack structure and a second vertical memory structure. The second stack structure includes second gate lines stacked in the vertical direction and extending in a second horizontal direction, perpendicular to the first horizontal direction. The second vertical memory structure penetrates through the second gate lines in the vertical direction.

公开(公告)号：US20210358910A1

公开(公告)日：2021-11-18

申请号：US17384920

申请日：2021-07-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongsoo LEE ,  Wonkeun CHUNG ,  Hoonjoo NA ,  Suyoung BAE ,  Jaeyeol SONG ,  Jonghan LEE ,  HyungSuk JUNG ,  Sangjin HYUN

IPC: H01L27/092 ,  H01L29/786 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/51 ,  H01L29/423

Abstract: Disclosed are semiconductor devices and methods of manufacturing the same. The semiconductor device comprises a first transistor on a substrate, and a second transistor on the substrate. Each of the first and second transistors includes a plurality of semiconductor patterns vertically stacked on the substrate and vertically spaced apart from each other, and a gate dielectric pattern and a work function pattern filling a space between the semiconductor patterns. The work function pattern of the first transistor includes a first work function metal layer, the work function pattern of the second transistor includes the first work function metal layer and a second work function metal layer, the first work function metal layer of each of the first and second transistors has a work function greater than that of the second work function metal layer, and the first transistor has a threshold voltage less than that of the second transistor.

公开(公告)号：US20180026112A1

公开(公告)日：2018-01-25

申请号：US15720812

申请日：2017-09-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Moonkyu PARK ,  Hoonjoo NA ,  Jaeyeol SONG ,  Sangjin HYUN

IPC: H01L29/49 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/423 ,  H01L27/092 ,  H01L21/8234

CPC classification number: H01L29/4966 ,  H01L21/82345 ,  H01L21/823821 ,  H01L21/823842 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/42364 ,  H01L29/42376 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/785

Abstract: A semiconductor device includes a semiconductor substrate having a first area and a second area, and a first gate pattern on the first area and a second gate pattern on the second area. The first gate pattern includes a first gate insulating pattern on the first area, a first gate barrier pattern on the first gate insulating pattern, and a first work function metal pattern on the first gate barrier pattern. The second gate pattern includes a second gate insulating pattern on the second area, a second gate barrier pattern on the second gate insulating pattern, and a second work function metal pattern on the second gate barrier pattern. The first gate barrier pattern includes a metal material different than the second gate barrier pattern.

公开(公告)号：US20220208706A1

公开(公告)日：2022-06-30

申请号：US17694035

申请日：2022-03-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Joohee JANG ,  Seokho KIM ,  Hoonjoo NA ,  Jaehyung PARK ,  Kyuha LEE

IPC: H01L23/00 ,  H01L27/146

Abstract: A method includes forming a first substrate including a first dielectric layer and a first metal pad, forming a second substrate including a second dielectric layer and a second metal pad, and bonding the first dielectric layer to the second dielectric layer, and the first metal pad to the second metal pad. One or both of the first and second substrates is formed by forming a first insulating layer, forming an opening in the layer, forming a barrier on an inner surface of the opening, forming a metal pad material on the barrier, polishing the metal pad material to expose a portion of the barrier and to form a gap, expanding the gap, forming a second insulating layer to fill the opening and the gap, and polishing the insulating layers such that a top surface of the metal pad is substantially planar with an upper surface of the polished layer.

公开(公告)号：US20220093567A1

公开(公告)日：2022-03-24

申请号：US17376784

申请日：2021-07-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinnam KIM ,  Seokho KIM ,  Hoonjoo NA ,  Kwangjin MOON

IPC: H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L23/48

Abstract: A semiconductor package includes a first structure including a first semiconductor chip, and a second structure on the first structure. The second structure includes a second semiconductor chip, a semiconductor pattern horizontally spaced apart from the second semiconductor chip and on a side surface of the second semiconductor chip, an insulating gap fill pattern between the second semiconductor chip and the semiconductor pattern, and through-electrode structures. At least one of the through-electrode structures penetrates through at least a portion of the second semiconductor chip or penetrates through the semiconductor pattern.

公开(公告)号：US20220020624A1

公开(公告)日：2022-01-20

申请号：US17218606

申请日：2021-03-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaehyun PHEE ,  Hoechul KIM ,  Seokho KIM ,  Taeyeong KIM ,  Hoonjoo NA

IPC: H01L21/68 ,  H01L21/67

Abstract: A wafer bonding apparatus including a first stage having a first surface and being configured to hold a first wafer on the first surface; a second stage having a second surface and being configured to hold a second wafer on the second surface facing the first surface; a first target image sensor on an outer portion of the first stage; a second target image sensor on an outer portion of the second stage; and a target portion on the first or second stage, the target portion having a target plate fixedly installed and spaced apart from the first or second target image sensor by a predetermined distance, wherein, in an alignment measurement of the first and second stages, the first and second stages are movable so that the first and second target image sensors face each other and the target plate is between the first and second target image sensors.

公开(公告)号：US20210391350A1

公开(公告)日：2021-12-16

申请号：US17160874

申请日：2021-01-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seungha OH ,  Weonhong KIM ,  Hoonjoo NA

IPC: H01L27/11578 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/108

Abstract: A three-dimensional semiconductor device includes a first substrate; a plurality of first transistors on the first substrate; a second substrate on the plurality of first transistors; a plurality of second transistors on the second substrate; and an interconnection portion electrically connecting the plurality of first transistors and the plurality of second transistors. Each of the plurality of first transistors includes a first gate insulating film on the first substrate and having a first hydrogen content. Each of the plurality of second transistors includes a second gate insulating film on the second substrate and having a second hydrogen content. The second hydrogen content is greater than the first hydrogen content.

公开(公告)号：US20200098711A1

公开(公告)日：2020-03-26

申请号：US16404841

申请日：2019-05-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ju-Il CHOI ,  Pil-Kyu KANG ,  Hoechul KIM ,  Hoonjoo NA ,  Jaehyung PARK ,  Seongmin SON

IPC: H01L23/00 ,  H01L25/16

Abstract: A semiconductor device and a semiconductor package, the device including a first buffer dielectric layer on a first dielectric layer; a second dielectric layer and a second buffer dielectric layer sequentially disposed on the first buffer dielectric layer, the second buffer dielectric layer being in contact with the first buffer dielectric layer; and a pad interconnection structure that penetrates the first buffer dielectric layer and the second buffer dielectric layer, wherein the pad interconnection structure includes copper and tin.

公开(公告)号：US20130043518A1

公开(公告)日：2013-02-21

申请号：US13633663

申请日：2012-10-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hoonjoo NA ,  Sangjin HYUN ,  Yugyun SHIN ,  Hongbae PARK ,  Sughun HONG ,  Hye-Lan LEE ,  Hyung-Seok HONG

IPC: H01L29/78

CPC classification number: H01L21/823842 ,  H01L29/66545

Abstract: A method of fabricating a semiconductor device includes forming an interlayer dielectric on a substrate, the interlayer dielectric including first and second openings respectively disposed in first and second regions formed separately in the substrate; forming a first conductive layer filling the first and second openings; etching the first conductive layer such that a bottom surface of the first opening is exposed and a portion of the first conductive layer in the second opening remains; and forming a second conductive layer filling the first opening and a portion of the second opening.

Abstract translation: 制造半导体器件的方法包括在衬底上形成层间电介质，所述层间电介质包括分别设置在所述衬底中分开形成的第一和第二区域中的第一和第二开口; 形成填充所述第一和第二开口的第一导电层; 蚀刻第一导电层，使得第一开口的底表面露出，并且第二开口中的第一导电层的一部分保留; 以及形成填充所述第一开口和所述第二开口的一部分的第二导电层。