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    SEMICONDUCTOR MEMORY DEVICE
    11.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 有权

    公开(公告)号：US20220199621A1

    公开(公告)日：2022-06-23

    申请号：US17541584

    申请日：2021-12-03

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kyunghwan Lee ,  Yongseok Kim ,  Ilgweon Kim ,  Huijung Kim ,  Sungwon Yoo ,  Minhee Cho

    IPC: H01L27/108

    Abstract: A semiconductor memory device includes: a first word line extending in a vertical direction; a second word line spaced apart from the first word line in a first horizontal direction and extending in the vertical direction; a first semiconductor pattern of a ring-shaped horizontal cross-section surrounding the first word line and constituting a portion of a first cell transistor; a second semiconductor pattern of a ring-shaped horizontal cross-section surrounding the second word line and constituting a portion of a second cell transistor; a cell capacitor between the first semiconductor pattern and the second semiconductor pattern and including a first electrode, a second electrode, and a capacitor dielectric film; a first bit line opposite the cell capacitor with respect to the first semiconductor pattern and extending in a second horizontal direction; and a second bit line opposite the cell capacitor with respect to the second semiconductor pattern.

    SEMICONDUCTOR DEVICES HAVING BURIED GATES
    12.
    发明申请
    SEMICONDUCTOR DEVICES HAVING BURIED GATES 有权

    公开(公告)号：US20220077154A1

    公开(公告)日：2022-03-10

    申请号：US17318563

    申请日：2021-05-12

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Huijung Kim ,  Minwoo Kwon ,  Sangyeon Han ,  Sangwon Kim ,  Junsoo Kim ,  Hyeonjin Shin ,  Eunkyu Lee

    IPC: H01L27/108 ,  H01L29/78 ,  H01L29/423

    Abstract: A semiconductor device includes a substrate including an active region, a gate structure disposed in a gate trench in the substrate, a bit line disposed on the substrate and electrically connected to the active region on one side of the gate structure, and a capacitor disposed on the bit line and electrically connected to the active region on another side of the gate structure. The gate structure includes a gate dielectric layer disposed on bottom and inner side surfaces of the gate trench, a conductive layer disposed on the gate dielectric layer in a lower portion of the gate trench, sidewall insulating layers disposed on the gate dielectric layer, on an upper surface of the conductive layer, a graphene conductive layer disposed on the conductive layer, and a buried insulating layer disposed between the sidewall insulating layers on the graphene conductive layer.

    INTEGRATED CIRCUIT DEVICE
    14.
    发明公开
    INTEGRATED CIRCUIT DEVICE 审中-公开

    公开(公告)号：US20230402518A1

    公开(公告)日：2023-12-14

    申请号：US18202085

    申请日：2023-05-25

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Taejin Park ,  Kyujin Kim ,  Bongsoo Kim ,  Huijung Kim ,  Pyung Moon ,  Chulkwon Park ,  Gyunghyun Yoon ,  Heejae Chae

    IPC: H01L29/423 ,  H10B12/00 ,  H01L29/49

    CPC classification number: H01L29/4236 ,  H10B12/315 ,  H01L29/4916

    Abstract: An integrated circuit (IC) device includes a gate trench formed inside a substrate, the gate trench including a bottom portion and a sidewall portion, a gate electrode structure disposed apart from the bottom portion and the sidewall portion of the gate trench, the gate electrode structure including a gate electrode including a first sub-gate electrode formed in a lower portion of the gate trench and a second sub-gate electrode formed on the first sub-gate electrode and a gate capping layer formed on the second sub-gate electrode, and a gate insulating layer formed between the gate trench and the gate electrode structure, the gate insulating layer including a base insulating layer formed between the bottom portion and the sidewall portion of the gate trench and the gate electrode structure and a reinforcing insulating layer formed on a sidewall portion of the second sub-gate electrode.

    Semiconductor devices including semiconductor pattern
    15.
    发明授权
    Semiconductor devices including semiconductor pattern 有权

    公开(公告)号：US11581316B2

    公开(公告)日：2023-02-14

    申请号：US17092593

    申请日：2020-11-09

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hyuncheol Kim ,  Yongseok Kim ,  Huijung Kim ,  Satoru Yamada ,  Sungwon Yoo ,  Kyunghwan Lee ,  Jaeho Hong

    IPC: H01L27/102 ,  H01L29/74

    Abstract: A semiconductor device includes a first conductive line and a second conductive line spaced apart from the first conductive line. A semiconductor pattern is disposed between the first conductive line and the second conductive line. The semiconductor pattern includes a first semiconductor pattern having first-conductivity-type impurities disposed adjacent to the first conductive line. A second semiconductor pattern having second-conductivity-type impurities is disposed adjacent to the second conductive line. A third semiconductor pattern is disposed between the first semiconductor pattern and the second semiconductor pattern. The third semiconductor pattern includes a first region disposed adjacent to the first semiconductor pattern and a second region disposed between the first region and the second semiconductor pattern. At least one of the first region and the second region comprises an intrinsic semiconductor layer. A first gate line crosses the first region and a second gate line crosses the second region.

    Electronic apparatus and operation method for predicting HVAC energy consumption
    16.
    发明授权
    Electronic apparatus and operation method for predicting HVAC energy consumption 有权

    公开(公告)号：US11536477B2

    公开(公告)日：2022-12-27

    申请号：US17004445

    申请日：2020-08-27

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hyeonje Cho ,  Inhwan Hwang ,  Huijung Kim ,  Yunhu Ji ,  Sehoon Kim

    IPC: F24F11/46 ,  F24F11/63 ,  F24F11/52 ,  F24F110/12 ,  F24F130/10 ,  F24F110/32 ,  F24F110/52 ,  F24F110/74 ,  F24F110/22

    Abstract: An operation method for reducing energy consumption and an electronic apparatus thereof are provided. The operation method includes obtaining, by the electronic apparatus, weather forecast information, inputting, by the electronic apparatus, the weather forecast information to an artificial intelligence model for predicting an amount of power to be consumed by a first air conditioner, and displaying, by the electronic apparatus, the predicted power consumption amount of the first air conditioner output from the artificial intelligence model, wherein the artificial intelligence model is trained to obtain correlation information between a weather condition and a power consumption amount of an air conditioner, based on a weather history and operations of a plurality of air conditioners related to the weather history, and predict the amount of power to be consumed by the first air conditioner based on the correlation information and the weather forecast information.

    Semiconductor devices including semiconductor pattern
    18.
    发明授权
    Semiconductor devices including semiconductor pattern 有权

    公开(公告)号：US12191136B2

    公开(公告)日：2025-01-07

    申请号：US18098174

    申请日：2023-01-18

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hyuncheol Kim ,  Yongseok Kim ,  Huijung Kim ,  Satoru Yamada ,  Sungwon Yoo ,  Kyunghwan Lee ,  Jaeho Hong

    IPC: H01L29/74 ,  H10B12/10

    Abstract: A semiconductor device includes a first conductive line and a second conductive line spaced apart from the first conductive line. A semiconductor pattern is disposed between the first conductive line and the second conductive line. The semiconductor pattern includes a first semiconductor pattern having first-conductivity-type impurities disposed adjacent to the first conductive line. A second semiconductor pattern having second-conductivity-type impurities is disposed adjacent to the second conductive line. A third semiconductor pattern is disposed between the first semiconductor pattern and the second semiconductor pattern. The third semiconductor pattern includes a first region disposed adjacent to the first semiconductor pattern and a second region disposed between the first region and the second semiconductor pattern. At least one of the first region and the second region comprises an intrinsic semiconductor layer. A first gate line crosses the first region and a second gate line crosses the second region.

    SEMICONDUCTOR MEMORY DEVICE
    19.
    发明公开
    SEMICONDUCTOR MEMORY DEVICE 审中-公开

    公开(公告)号：US20240224494A1

    公开(公告)日：2024-07-04

    申请号：US18414893

    申请日：2024-01-17

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kyunghwan Lee ,  Yongseok Kim ,  Ilgweon Kim ,  Huijung Kim ,  Sungwon Yoo ,  Minhee Cho

    IPC: H10B12/00

    CPC classification number: H10B12/00

    Abstract: A semiconductor memory device includes: a first word line extending in a vertical direction; a second word line spaced apart from the first word line in a first horizontal direction and extending in the vertical direction; a first semiconductor pattern of a ring-shaped horizontal cross-section surrounding the first word line and constituting a portion of a first cell transistor; a second semiconductor pattern of a ring-shaped horizontal cross-section surrounding the second word line and constituting a portion of a second cell transistor; a cell capacitor between the first semiconductor pattern and the second semiconductor pattern and including a first electrode, a second electrode, and a capacitor dielectric film; a first bit line opposite the cell capacitor with respect to the first semiconductor pattern and extending in a second horizontal direction; and a second bit line opposite the cell capacitor with respect to the second semiconductor pattern.

    Semiconductor device including carbon-containing contact fence
    20.
    发明授权
    Semiconductor device including carbon-containing contact fence 有权

    公开(公告)号：US11980025B2

    公开(公告)日：2024-05-07

    申请号：US17705991

    申请日：2022-03-28

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Junhyeok Ahn ,  Huijung Kim ,  Kiseok Lee ,  Myeongdong Lee

    IPC: H10B12/00

    CPC classification number: H10B12/485 ,  H10B12/34 ,  H10B12/482 ,  H10B12/488

    Abstract: A semiconductor device includes; an active region defined by an isolation film on a substrate, a word line in the substrate, the word line extending in a first direction and crossing the active region, a bit line above the word line and extending in a second direction, a contact between bit lines adjacent in the first direction, the contact connecting the active region and extending in a vertical direction, and a contact fence disposed on each of opposing side surfaces of the contact in the second direction and extending in the vertical direction, wherein the active region has a bar shape extending oblique to the first direction, and the contact fence includes a carbon-containing insulating film.

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