公开(公告)号：US11201172B2

公开(公告)日：2021-12-14

申请号：US17153939

申请日：2021-01-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-Woo Seo ,  Ki-Man Park ,  Ha-Young Kim ,  Junghwan Shin ,  Keunho Lee ,  Sungwe Cho

IPC: H03K3/356 ,  H01L27/118 ,  H01L27/02 ,  H03K3/3562

Abstract: Disclosed is a semiconductor device including a substrate with first and second regions adjacent to each other in a first direction, and first to third gate electrodes extending from the first region toward the second region. Each of the first and second regions includes a PMOSFET region and an NMOSFET region. The first to third gate electrodes extend in the first direction and are sequentially arranged in a second direction different from the first direction. The first and third gate electrodes are supplied with a first signal. The second gate electrode is supplied with a second signal that is an inverted signal of the first signal. The first gate electrode includes a first gate of the first region and a first gate of the second region. The first gates are aligned and connected with each other in the first direction.

公开(公告)号：US11043428B2

公开(公告)日：2021-06-22

申请号：US16450383

申请日：2019-06-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ha-Young Kim ,  Jin Tae Kim ,  Jae-Woo Seo ,  Dong-yeon Heo

IPC: H01L27/02 ,  H01L21/8234 ,  G06F30/392 ,  H01L21/768 ,  G06F30/398 ,  H01L21/8238 ,  H01L27/06

Abstract: A method of manufacturing a semiconductor device includes configuring a layout pattern; and forming conductive lines corresponding to the layout pattern on a substrate, wherein configuring the layout pattern includes: arranging pre-conductive patterns and post-conductive patterns for a first logic cell, a second logic cell, and a third logic cell; rearranging the pre-conductive patterns and the post-conductive patterns so that two conductive patterns that are adjacent to a boundary between two adjacent logic cells from among the first logic cell, the second logic cell, and the third logic cell are formed by different photolithography processes; and arranging conductive patterns for a dummy cell arranged between the second logic cell and the third logic cell.

公开(公告)号：US11031385B2

公开(公告)日：2021-06-08

申请号：US16725023

申请日：2019-12-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-Woo Seo ,  Jin Tae Kim ,  Tae Joong Song ,  Hyoung-Suk Oh ,  Keun Ho Lee ,  Dal Hee Lee ,  Sung We Cho

IPC: H01L27/02 ,  H01L27/088 ,  H01L21/67 ,  H01L21/8234 ,  H01L23/522 ,  H01L23/528 ,  H03K19/17736 ,  H03K19/17764 ,  H01L27/118 ,  H01L27/092 ,  H03K19/00 ,  H03K19/20 ,  H03K19/21

Abstract: An integrated circuit including a first standard cell including, first transistors, the first transistors being first unfolded transistors, a first metal pin, a second metal pin, and a third metal pin on a first layer, the first metal pin and the second metal pin having a first minimum metal center-to-metal center pitch therebetween less than or equal to 80 nm, a fourth metal pin and a fifth metal pin at a second layer, the fourth metal pin and the fifth metal pin extending in a second direction, the second direction being perpendicular to the first direction, a first via between the first metal pin and the fourth metal pin, and a second via between the third metal pin and the fifth metal pin such that a first via center-to-via center space between the first via and the second via is greater than double the first minimum metal center-to-metal center pitch.

公开(公告)号：US10691859B2

公开(公告)日：2020-06-23

申请号：US15908291

申请日：2018-02-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jae-Woo Seo ,  Ha-Young Kim ,  Hyun-Jeong Roh

IPC: G06F30/392 ,  G03F1/70 ,  H01L21/311 ,  G03F7/20 ,  G06F30/00 ,  G06F30/39 ,  G06F119/18

Abstract: A method of designing a layout of an integrated circuit (IC) includes placing a first cell in the layout, placing a second cell in the layout adjacent to the first cell at a first boundary between the first and second cells, and generating a plurality of commands executable by a processor to form a semiconductor device based on the layout. The first cell includes a first pattern and a second pattern. The first and second patterns are adjacent to the first boundary, the first and second patterns have different colors, and a first boundary space between the first pattern and the first boundary is different from a second boundary space between the second pattern and the first boundary.

公开(公告)号：US10332798B2

公开(公告)日：2019-06-25

申请号：US15624039

申请日：2017-06-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ha-Young Kim ,  JinTae Kim ,  Jae-Woo Seo ,  Dong-yeon Heo

IPC: H01L21/8238 ,  H01L27/06 ,  G06F17/50 ,  H01L21/8234 ,  H01L21/768 ,  H01L27/02

Abstract: A method of manufacturing a semiconductor device includes configuring a layout pattern; and forming conductive lines corresponding to the layout pattern on a substrate, wherein configuring the layout pattern includes: arranging pre-conductive patterns and post-conductive patterns for a first logic cell, a second logic cell, and a third logic cell; rearranging the pre-conductive patterns and the post-conductive patterns so that two conductive patterns that are adjacent to a boundary between two adjacent logic cells from among the first logic cell, the second logic cell, and the third logic cell are formed by different photolithography processes; and arranging conductive patterns for a dummy cell arranged between the second logic cell and the third logic cell.

公开(公告)号：US09946828B2

公开(公告)日：2018-04-17

申请号：US14926128

申请日：2015-10-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jin-Tae Kim ,  Ha-Young Kim ,  Jae-Woo Seo

IPC: G06F17/50

CPC classification number: G06F17/5072 ,  G06F17/5081

Abstract: A method of designing a layout of an integrated circuit (IC), which is implemented by a computer system or a processor, includes receiving input layout data, and performing a design rule check with regard to a plurality of patterns. The method includes, merging, from among a first pattern and a second pattern against the design rule, the first pattern with a third pattern connected to a same net as the first pattern, and generating output layout data.

公开(公告)号：US09698056B2

公开(公告)日：2017-07-04

申请号：US15094764

申请日：2016-04-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ha-Young Kim ,  Jin Tae Kim ,  Jae-Woo Seo ,  Dong-yeon Heo

IPC: H01L27/06 ,  H01L21/768 ,  G06F17/50 ,  H01L21/8234 ,  H01L27/02 ,  H01L21/8238

CPC classification number: H01L21/823475 ,  G06F17/5072 ,  G06F17/5081 ,  H01L21/76816 ,  H01L21/76892 ,  H01L21/823871 ,  H01L27/0207 ,  H01L27/0629

Abstract: A method of manufacturing a semiconductor device includes providing pre-conductive lines and post-conductive lines for forming a first logic cell and a second logic cell, which are adjacent to each other, and a dummy cell and a third logic cell, which are adjacent to each other. A first conductive line, adjacent to the second logic cell, from among conductive lines of the first logic cell is spaced a first reference distance apart from a second conductive line, adjacent to the first logic cell, from among conductive lines of the second logic cell. A dummy line, which is adjacent to the third logic cell, from among conductive lines of the dummy cell is spaced a second reference distance apart from a third conductive line, which is adjacent to the dummy cell, from among conductive lines of the third logic cell. The second reference distance is greater than the first reference distance.

公开(公告)号：US11764201B2

公开(公告)日：2023-09-19

申请号：US17158109

申请日：2021-01-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji Su Yu ,  Jae-Woo Seo ,  Sanghoon Baek ,  Hyeon Gyu You

IPC: H01L27/02 ,  H01L23/528 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  G06F30/392

CPC classification number: H01L27/0207 ,  G06F30/392 ,  H01L23/5286 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/78618 ,  H01L29/78696

Abstract: An integrated circuit including a plurality of standard cells is provided. The integrated circuit includes a first standard cell group including at least two first standard cells, a second standard cell group adjacent to the first standard cell group in a first direction, the second standard cell group including at least one second standard cell, and a first insulating gate bordered by one side of at least one of the first standard cells and one side of the at least one second standard cell, wherein each of the first and second standard cells includes a p-type transistor (pFET) and an n-type transistor (nFET) which are integrated, wherein each of the first and second standard cells has first wiring lines of different designs, and wherein each of the first and second standard cells has the same or different placement of an active region according to the corresponding design.

公开(公告)号：US10930675B2

公开(公告)日：2021-02-23

申请号：US16669639

申请日：2019-10-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-Woo Seo ,  Ki-Man Park ,  Ha-Young Kim ,  Junghwan Shin ,  Keunho Lee ,  Sungwe Cho

IPC: H03K3/289 ,  H01L27/118 ,  H01L27/02 ,  H03K3/3562

Abstract: Disclosed is a semiconductor device including a substrate with first and second regions adjacent to each other in a first direction, and first to third gate electrodes extending from the first region toward the second region. Each of the first and second regions includes a PMOSFET region and an NMOSFET region. The first to third gate electrodes extend in the first direction and are sequentially arranged in a second direction different from the first direction. The first and third gate electrodes are supplied with a first signal. The second gate electrode is supplied with a second signal that is an inverted signal of the first signal. The first gate electrode includes a first gate of the first region and a first gate of the second region. The first gates are aligned and connected with each other in the first direction.

公开(公告)号：US10911034B2

公开(公告)日：2021-02-02

申请号：US16679794

申请日：2019-11-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-Woo Seo ,  Youngsoo Shin ,  Jinwook Jung

IPC: H03K3/3562 ,  H01L27/02 ,  G01R31/317 ,  G01R31/3185 ,  H03K3/037

Abstract: A semiconductor device may include a clock driver including a first gate line, a second gate line, a third gate line and a fourth gate line each extending in a first direction, the first gate line and the second gate line each configured to receive a clock signal, and the third gate line and the fourth gate line each configured to receive an inverted clock signal; a master latch circuit overlapping the first gate line and the third gate line such that the master latch circuit receive the clock signal from the first gate line and receive the inverted clock signal from the third gate line; and a slave latch circuit overlapping the second gate line and the fourth gate line such that the slave latch circuit receives the clock signal from the second gate line, and receives the inverted clock signal from the fourth gate line.