公开(公告)号：US09012320B2

公开(公告)日：2015-04-21

申请号：US14258436

申请日：2014-04-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaegoo Lee ,  Kil-Su Jeong ,  Hansoo Kim ,  Youngwoo Park

IPC: H01L27/115

CPC classification number: H01L23/52 ,  H01L27/1157 ,  H01L27/11578 ,  H01L27/11582 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Example embodiments relate to a three-dimensional semiconductor memory device including an electrode structure on a substrate, the electrode structure including at least one conductive pattern on a lower electrode, and a semiconductor pattern extending through the electrode structure to the substrate. A vertical insulating layer may be between the semiconductor pattern and the electrode structure, and a lower insulating layer may be between the lower electrode and the substrate. The lower insulating layer may be between a bottom surface of the vertical insulating layer and a top surface of the substrate. Example embodiments related to methods for fabricating the foregoing three-dimensional semiconductor memory device.

Abstract translation: 示例实施例涉及一种三维半导体存储器件，其包括在衬底上的电极结构，该电极结构包括在下电极上的至少一个导电图案，以及半导体图案，其延伸穿过该电极结构到该衬底。 垂直绝缘层可以在半导体图案和电极结构之间，下绝缘层可以位于下电极和衬底之间。 下绝缘层可以在垂直绝缘层的底表面和基板的顶表面之间。 与制造上述三维半导体存储器件的方法相关的示例实施例。

公开(公告)号：US11588035B2

公开(公告)日：2023-02-21

申请号：US16998342

申请日：2020-08-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaegoo Lee

IPC: H01L29/423 ,  H01L27/11556 ,  H01L27/11582

Abstract: A semiconductor device includes a substrate having a first region and a second region, gate electrodes stacked in the first region and forming a pad region having a stepped shape extending by different lengths in the second region, interlayer insulating layers alternately stacked with the gate electrodes, channel structures passing through the gate electrodes in the first region and including a channel layer, separation regions passing through the gate electrodes in the first and second regions, an etch-stop layer disposed on uppermost gate electrodes, among the gate electrodes forming the pad region in the second region, not to overlap the first region and the separation regions, a cell region insulating layer covering the gate electrodes and the etch-stop layer, and contact plugs passing through the cell region insulating layer and the etch-stop layer in the second region and connected to the gate electrodes in the pad region.

公开(公告)号：US09142563B2

公开(公告)日：2015-09-22

申请号：US14599621

申请日：2015-01-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung-Il Chang ,  Youngwoo Park ,  Jaegoo Lee

IPC: H01L29/792 ,  H01L27/115 ,  H01L21/311

CPC classification number: H01L27/11582 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/31111 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11578 ,  H01L29/42324 ,  H01L29/4234

Abstract: A 3D semiconductor device includes an electrode structure has electrodes stacked on a substrate, semiconductor patterns penetrating the electrode structure, charge storing patterns interposed between the semiconductor patterns and the electrode structure, and blocking insulating patterns interposed between the charge storing patterns and the electrode structure. Each of the blocking insulating patterns surrounds the semiconductor patterns, and the charge storing patterns are horizontally spaced from each other and configured in such a way as to each be disposed around a respective one of the semiconductor patterns. Also, each of the charge storing patterns includes a plurality of horizontal segments, each interposed between vertically adjacent ones of the electrodes.

公开(公告)号：US20150037949A1

公开(公告)日：2015-02-05

申请号：US14516996

申请日：2014-10-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaegoo Lee

IPC: H01L27/115

CPC classification number: H01L27/11563 ,  G11C16/0408 ,  G11C16/0483 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582

Abstract: Methods of fabricating a semiconductor device are provided. The method includes alternately stacking first material layers and second material layers on a substrate to form a stacked structure, forming a through hole penetrating the stacked structure, forming a data storage layer on a sidewall of the through hole, forming a semiconductor pattern electrically connected to the substrate on an inner sidewall of the data storage layer, etching an upper portion of the data storage layer to form a first recessed region exposing an outer sidewall of the semiconductor pattern, and forming a first conductive layer in the first recessed region. Related devices are also disclosed.

Abstract translation: 提供制造半导体器件的方法。 该方法包括在基板上交替堆叠第一材料层和第二材料层以形成层叠结构，形成穿透层叠结构的通孔，在通孔的侧壁上形成数据存储层，形成电连接到 在数据存储层的内侧壁上的衬底，蚀刻数据存储层的上部以形成暴露半导体图案的外侧壁的第一凹部，以及在第一凹陷区域中形成第一导电层。 还公开了相关设备。

公开(公告)号：US12046565B2

公开(公告)日：2024-07-23

申请号：US17378831

申请日：2021-07-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaegoo Lee

IPC: H01L23/00 ,  H01L23/535 ,  H10B43/27 ,  H10B43/40

CPC classification number: H01L23/562 ,  H01L23/535 ,  H10B43/27 ,  H10B43/40

Abstract: A vertical memory device includes a cell stacked structure on a substrate, a support structure and cell contact plugs. The cell stacked structure includes gate patterns spaced apart from each other in a vertical direction and insulation layers between the gate patterns. The gate patterns extend in a first direction, and edges of the gate patterns along the first direction include step portions having step shape. The support structure passes through the cell stacked structure and the step portion of one of the gate patterns, and includes a spacer layer having cup shape, first metal patterns having ring shape, and a second metal pattern filling an inner space of the spacer layer. The cell contact plugs are on the step portions. The first metal patterns are at the same vertical levels of the gate patterns. Sidewalls of the first metal patterns are adjacent to sidewalls of the gate patterns.

公开(公告)号：US10741577B2

公开(公告)日：2020-08-11

申请号：US16180781

申请日：2018-11-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Bongyong Lee ,  Jaegoo Lee

IPC: H01L27/11582 ,  H01L27/11568 ,  H01L29/423 ,  H01L29/417 ,  H01L27/11565 ,  H01L29/10 ,  H01L29/66 ,  H01L21/266 ,  H01L21/265 ,  H01L21/3105

Abstract: A three-dimensional semiconductor memory device may include a substrate comprising a cell array region and a connection region, an electrode structure including a plurality of gate electrodes sequentially stacked on a surface of the substrate and extending from the cell array region to the connection region, a first source conductive pattern between the electrode structure and the substrate on the cell array region, and a cell vertical semiconductor pattern and a first dummy vertical semiconductor pattern that penetrate the electrode structure and the first source conductive pattern and extend into the substrate. The cell vertical semiconductor pattern may contact the first source conductive pattern. The first dummy vertical semiconductor pattern may be electrically insulated from the first source conductive pattern.

公开(公告)号：US20190326315A1

公开(公告)日：2019-10-24

申请号：US16180781

申请日：2018-11-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Bongyong Lee ,  Jaegoo Lee

IPC: H01L27/11582 ,  H01L27/11568 ,  H01L29/423 ,  H01L29/417 ,  H01L29/10 ,  H01L27/11565

Abstract: A three-dimensional semiconductor memory device may include a substrate comprising a cell array region and a connection region, an electrode structure including a plurality of gate electrodes sequentially stacked on a surface of the substrate and extending from the cell array region to the connection region, a first source conductive pattern between the electrode structure and the substrate on the cell array region, and a cell vertical semiconductor pattern and a first dummy vertical semiconductor pattern that penetrate the electrode structure and the first source conductive pattern and extend into the substrate. The cell vertical semiconductor pattern may contact the first source conductive pattern. The first dummy vertical semiconductor pattern may be electrically insulated from the first source conductive pattern.

公开(公告)号：US09559112B2

公开(公告)日：2017-01-31

申请号：US14472952

申请日：2014-08-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaegoo Lee ,  Youngwoo Park ,  Jungdal Choi

IPC: H01L27/115 ,  H01L29/78 ,  H01L29/423 ,  H01L29/792

CPC classification number: H01L27/11578 ,  H01L27/11582 ,  H01L29/4234 ,  H01L29/7827 ,  H01L29/7926

Abstract: A method of fabricating a semiconductor memory device includes forming a mold stack on a substrate and the mold stack including first sacrificial layers and second sacrificial layers alternately stacked on the substrate. The method also includes forming a plurality of vertical channels that penetrate the mold stack and that contact the substrate, patterning the mold stack to form word line cuts between the vertical channels, the word line cuts exposing the substrate, removing one of the first and second sacrificial layers to form recessed regions in the mold stack, forming a data storage layer, at least a portion of the data storage layer being formed between the vertical channels and the gates, forming gates in the recessed regions, forming air gaps between the gates by removing the other of the first and second sacrificial layers, and forming an insulation layer pattern in the word line cuts.

Abstract translation: 一种制造半导体存储器件的方法包括在衬底上形成模具堆叠，并且模具叠层包括交替层叠在衬底上的第一牺牲层和第二牺牲层。 该方法还包括形成多个垂直通道，其穿过模具叠层并与衬底接触，图案化模具叠层以形成垂直通道之间的字线切口，字线切割暴露衬底，去除第一和第二 牺牲层，以在模具堆叠中形成凹陷区域，形成数据存储层，数据存储层的至少一部分形成在垂直沟道和栅极之间，在凹陷区域中形成栅极，在栅极之间形成气隙，通过 去除第一和第二牺牲层中的另一个，并且在字线切割中形成绝缘层图案。

公开(公告)号：US09437483B2

公开(公告)日：2016-09-06

申请号：US14218091

申请日：2014-03-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaegoo Lee ,  Youngwoo Park

IPC: H01L21/4763 ,  H01L21/768 ,  H01L27/115

CPC classification number: H01L21/76832 ,  H01L27/11519 ,  H01L27/11548 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11575 ,  H01L27/11578 ,  H01L27/11582

Abstract: A plurality of vertical channels of semiconductor material are formed to extend in a vertical direction through the plurality of insulation layers and the plurality of conductive patterns, a gate insulating layer between the conductive pattern and the vertical channels that insulates the conductive pattern from the vertical channels. Conductive contact regions of the at least two of the conductive patterns are in a stepped configuration. An etch stop layer is positioned on the conductive contact regions, wherein the etch stop layer has a first portion on a first one of the plurality of conductive patterns and has a second portion on a second one of the plurality of conductive patterns, wherein the first portion is of a thickness that is greater than a thickness of the second portion.

Abstract translation: 多个垂直通道的半导体材料形成为沿着垂直方向延伸穿过多个绝缘层和多个导电图案，导电图案和垂直沟道之间的栅极绝缘层将导电图案与垂直沟道绝缘 。 至少两个导电图案的导电接触区域处于阶梯状结构。 蚀刻停止层位于导电接触区域上，其中蚀刻停止层在多个导电图案中的第一个上具有第一部分，并且在多个导电图案中的第二个导电图案上具有第二部分，其中第一部分 部分的厚度大于第二部分的厚度。

公开(公告)号：US09130054B2

公开(公告)日：2015-09-08

申请号：US13800872

申请日：2013-03-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byong-hyun Jang ,  Juhyung Kim ,  Woonkyung Lee ,  Jaegoo Lee ,  Chaeho Kim ,  Junkyu Yang ,  Phil Ouk Nam ,  Jaeyoung Ahn ,  Kihyun Hwang

IPC: H01L21/20 ,  H01L29/792 ,  H01L29/66 ,  H01L27/115

CPC classification number: H01L29/792 ,  H01L23/528 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/045 ,  H01L29/1037 ,  H01L29/42364 ,  H01L29/511 ,  H01L29/66833 ,  H01L29/7926 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor memory device and a method of fabricating the same. The device includes a plurality of gates vertically stacked on a top surface of a substrate with an epitaxial layer formed in the substrate, a vertical channel vertically penetrating the gates to be electrically connected to the epitaxial layer, and a memory layer provided between the vertical channel and the gates. The epitaxial layer has a top surface positioned at a level between a bottom surface of the lowermost one of the gates and the top surface of the substrate.

Abstract translation: 一种半导体存储器件及其制造方法。 该器件包括垂直堆叠在衬底的顶表面上的多个栅极，该衬底的顶表面上形成有在该衬底中形成的外延层，垂直穿过该栅极的垂直沟道以与该外延层电连接;以及存储层，设置在该垂直沟道 和大门。 外延层具有位于最下面一个栅极的底表面和基板的顶表面之间的高度的顶表面。